Verilog_Louis/Semaine_4/FIFO/tests/verilog/tb_fifo.v

`timescale 1ns/1ps

module tb_fifo;

    reg clk = 0;
    

    always #18.5 clk = ~clk;

    

    initial begin
        $dumpfile("runs/fifo.vcd");
        $dumpvars(0, tb_fifo);

        
    end

endmodule