Verilog_Louis/Semaine_7/DHT11/tests/verilog/tb_dht11.v

`timescale 1ns/1ps

module tb_dht11;

    reg clk = 0;
    always #18.5 clk = ~clk; // Génère une clock 27 MHz

    // === Registres ===
    wire        io_dht11_sig;
    reg         dht11_start;
    wire        dht11_data_ready;
    wire        dht11_busy;
    wire [7:0]  dht11_temp_data;
    wire [7:0]  dht11_hum_data;
    wire        dht11_error;

    // === Simulation du module DHT11 ===
    dht11_model dht11_model (
        .data(io_dht11_sig),
        .clk(clk),
        .rst_n(1'b1) // Reset non utilisé dans ce test
    );

    // === Module DHT11 INTERFACE ===
    dht11_interface dht11_interface (
        .i_clk(clk),
        .io_dht11_sig(io_dht11_sig),
        .i_start(dht11_start),
        .o_dht11_data_ready(dht11_data_ready),
        .o_busy(dht11_busy),
        .o_temp_data(dht11_temp_data),
        .o_hum_data(dht11_hum_data),
        .o_dht11_error(dht11_error)
    );

    pullup(io_dht11_sig);

    // === TEST SEQUENCE ===
    initial begin
        $dumpfile("runs/sim.vcd");
        $dumpvars(0, tb_dht11);
        dht11_start = 0;

        $display("==== Start DHT11 Test ====");
        
        #100;
        dht11_start = 1; // Démarre la lecture des données
        $display("DHT11 start...");

        wait(dht11_busy); // Attend que le module soit occupé
        $display("DHT11 busy...");

        dht11_start = 0;

        wait(dht11_data_ready); // Attend que les données soient prêtes
        $display("DHT11 data ready...");

        $display("Température : %d.%d °C", dht11_temp_data);
        $display("Humidité : %d.%d %%", dht11_hum_data);

        $display("==== End DHT11 Test ====");
        $finish;
    end

endmodule