forked from tanchou/Verilog
65 lines
1.6 KiB
Verilog
65 lines
1.6 KiB
Verilog
`timescale 1ns/1ps
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module tb_dht11;
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reg clk = 0;
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always #18.5 clk = ~clk; // Génère une clock 27 MHz
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// === Registres ===
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wire io_dht11_sig;
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reg dht11_start;
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wire dht11_data_ready;
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wire dht11_busy;
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wire [7:0] dht11_temp_data;
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wire [7:0] dht11_hum_data;
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wire dht11_error;
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// === Simulation du module DHT11 ===
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dht11_model dht11_model (
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.data(io_dht11_sig),
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.clk(clk),
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.rst_n(1'b1) // Reset non utilisé dans ce test
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);
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// === Module DHT11 INTERFACE ===
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dht11_interface dht11_interface (
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.i_clk(clk),
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.io_dht11_sig(io_dht11_sig),
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.i_start(dht11_start),
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.o_dht11_data_ready(dht11_data_ready),
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.o_busy(dht11_busy),
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.o_temp_data(dht11_temp_data),
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.o_hum_data(dht11_hum_data),
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.o_dht11_error(dht11_error)
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);
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pullup(io_dht11_sig);
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// === TEST SEQUENCE ===
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initial begin
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$dumpfile("runs/sim.vcd");
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$dumpvars(0, tb_dht11);
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dht11_start = 0;
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$display("==== Start DHT11 Test ====");
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#100;
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dht11_start = 1; // Démarre la lecture des données
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$display("DHT11 start...");
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wait(dht11_busy); // Attend que le module soit occupé
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$display("DHT11 busy...");
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dht11_start = 0;
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wait(dht11_data_ready); // Attend que les données soient prêtes
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$display("DHT11 data ready...");
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$display("Température : %d.%d °C", dht11_temp_data);
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$display("Humidité : %d.%d %%", dht11_hum_data);
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$display("==== End DHT11 Test ====");
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$finish;
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end
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endmodule |