Verilog_Louis/Semaine_4/FIFO/tests/verilog/tb_fifo.v

`timescale 1ns/1ps

module tb_fifo;

    reg clk = 0;
    
    reg wr_en = 0;
    reg rd_en = 0;
    reg [7:0] wr_data = 0;
    wire [7:0] rd_data;
    wire full;
    wire empty;

    always #18.5 clk = ~clk;

    fifo #(
        .DETPH(16),
        .WIDTH(8)
    ) fifo_inst (
        .clk(clk),
        .wr_en(wr_en),
        .wr_data(wr_data),
        .rd_en(rd_en),
        .rd_data(rd_data),
        .full(full),
        .empty(empty)
    );

    initial begin
        $dumpfile("runs/fifo.vcd");
        $dumpvars(0, tb_fifo);

        wr_en = 1;
        wr_data = 8'hAA;

        #37.0;

        wr_en = 0;

        #37.0;

        wr_en = 1;
        wr_data = 8'hBB;

        #37.0;

        wr_en = 0;

        #37.0;

        wr_en = 1;
        wr_data = 8'hCC;

        #37.0;

        wr_en = 0;

        #37.0;

        $display("rd_data: %h", rd_data);

        rd_en = 1;
        $display("rd_data: %h", rd_data);
        #37.0;

        rd_en = 0;

        #37.0;

        rd_en = 1;
        $display("rd_data: %h", rd_data);
        #37.0;
        rd_en = 0;

        #37.0;
        
        rd_en = 1;
        $display("rd_data: %h", rd_data);
        #37.0;
        rd_en = 0;

        #37.0;

        rd_en = 1;
        $display("rd_data: %h", rd_data);
        #19.0;
        rd_en = 0;
        
        #37.0;


        $finish;
        
    end

endmodule