Verilog_Louis/Semaine_1/UART/top_uart_rx_tx.v

module top_uart_rx_tx(
    input wire clk,
    input wire start, // Commencer l'ecriture
    input wire [7:0] data_in,
    input wire rx,
    output wire [7:0] data_out, 
    output wire valid, // Si 1 alors on peut lire 
    output wire tx
);

    parameter CLK_FREQ = 27_000_000;
    parameter BAUD_RATE = 115_200;

    uart_tx #(
        .CLK_FREQ(CLK_FREQ),
        .BAUD_RATE(BAUD_RATE)
    ) tx_instance (
        .clk(clk),
        .start(start),
        .data(data_in),
        .tx(tx)
    );

    uart_rx #(
        .CLK_FREQ(CLK_FREQ),
        .BAUD_RATE(BAUD_RATE)
    ) rx_instance (
        .clk(clk),
        .rx(rx),      
        .data(data_out),   
        .valid(valid)     
    );

endmodule