Verilog_Louis/Semaine 1/Capteur_recule_bidirectionel/tb_top_ultrasonic_led.v

`timescale 1ns/1ps

module tb_top_ultrasonic_led;

    reg clk;
    reg rst;
    reg start;
    reg echo;
    wire trig;
    wire [5:0] leds;

    // Instance du module top
    top_ultrasonic_led uut (
        .clk(clk),
        .rst(rst),
        .start(start),
        .echo(echo),
        .trig(trig),
        .leds(leds)
    );

    always #18.5 clk = ~clk;

    initial begin
        // Initialisation
        $dumpfile("top_ultrasonic_led.vcd");
        $dumpvars(0, tb_top_ultrasonic_led);

        clk = 0;
        rst = 1;
        start = 0;
        echo = 0;

        #100;      
        rst = 0;

        #50;
        start = 1;  
        #20;
        start = 0;

        // Attente du signal trig
        wait (trig == 1);
        $display("TRIG HIGH at %t", $time);
        wait (trig == 0);
        $display("TRIG LOW at %t", $time);

        repeat (500) @(posedge clk);
        echo = 1;
        #12000

        echo = 0;

        repeat (500) @(posedge clk);

        $display("Leds allumer : %b", leds);

        $finish;
    end

endmodule