forked from tanchou/Verilog
55f9161dfa
- Implemented the uart_tx module for UART transmission with configurable clock frequency and baud rate. - Added a testbench (uart_tx_tb) to verify the functionality of the uart_tx module, including signal generation for start, data, and clock. - Created a backup of the previous testbench (uart_tx_tb_old) for reference.
Verilog
Commands
Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc