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Verilog_Louis/Semaine_5/DHT11_LEDS/src/verilog/dht11_leds.v

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module dht11_leds (
input wire clk, // 27 MHz
inout wire dht11_sig,
input wire start,
output reg [5:0] leds
);
// === Registres ===
wire io_dht11_sig;
reg dht11_start;
wire dht11_data_ready;
wire dht11_busy;
wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data;
wire dht11_error;
dht11_interface dht11_interface (
.i_clk(clk),
.io_dht11_sig(io_dht11_sig),
.i_start(dht11_start),
.o_dht11_data_ready(dht11_data_ready),
.o_busy(dht11_busy),
.o_temp_data(dht11_temp_data),
.o_hum_data(dht11_hum_data),
.o_dht11_error(dht11_error)
);
initial begin
dht11_start = 0;
leds = 6'b000000;
end
always @(posedge clk) begin
if (start) begin
dht11_start = 1; // Démarre la lecture des données
leds[0] = 1; // LED verte allumée
end else begin
dht11_start = 0; // Arrête la lecture des données
leds[0] = 0; // LED verte éteinte
end
if (dht11_busy) begin
leds[1] = 1; // LED jaune allumée
end else begin
leds[1] = 0; // LED jaune éteinte
end
if (dht11_data_ready) begin
leds = {dht11_temp_data[7:4], dht11_hum_data[7:4]}; // Affiche les données sur les LEDs
end
if (dht11_error) begin
leds[5:3] = 3'b111; // Toutes les LEDs allumées en cas d'erreur
end else begin
leds[5:3] = 3'b000; // Éteint les LEDs si pas d'erreur
end
end
endmodule