forked from tanchou/Verilog
17 lines
582 B
Batchfile
17 lines
582 B
Batchfile
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@echo off
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rem https://github.com/YosysHQ/apicula
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set file_name=src\verilog\counter.v src\verilog\blink.v src\verilog\blink_top.v
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set constraints_file=constraints\blink_led.cst
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yosys -p "read_verilog -sv %file_name%; synth_gowin -json runs\blink_led_c.json"
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set DEVICE=GW2AR-LV18QN88C8/I7
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set BOARD=tangnano20k
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nextpnr-himbaechel --json runs\blink_led_c.json --write runs\pnr_blink_led.json --device %DEVICE% --vopt cst=%constraints_file% --vopt family=GW2A-18C
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gowin_pack -d %DEVICE% -o runs\blink_led_c.fs runs\pnr_blink_led.json
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rem openfpgaloader -b %BOARD% blink_led_c.fs
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