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Update testbench and simulation scripts to use a unified output file name for GTKWave

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Gamenight77
2025-05-19 09:31:53 +02:00
parent 75d1ff029b
commit 1006b77e95
5 changed files with 6 additions and 6 deletions
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2
Semaine_4/UART_FIFO/scripts/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off
echo === Lancement de GTKWave ===
gtkwave runs/uart_tx_fifo.vcd
gtkwave runs/sim.vcd

2
Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp
:: Top-level testbench module
set TOP=tb_uart_tx_fifo
set TOP=tb_uart_rx_fifo
:: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog