Update testbench and simulation scripts to use a unified output file name for GTKWave

Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v

@@ -45,7 +45,7 @@ module tb_uart_fifo;
     );
 
     initial begin
-        $dumpfile("runs/uart_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_fifo);
 
         $display("======== Start UART LOOPBACK test =========");

Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v

@@ -42,7 +42,7 @@ module tb_uart_rx_fifo;
     always #(CLK_PERIOD_NS/2) clk = ~clk;
 
     initial begin
-        $dumpfile("runs/uart_rx_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_rx_fifo);
         $display("======== Start UART RX FIFO test =========");
         #100; 
@@ -69,7 +69,7 @@ module tb_uart_rx_fifo;
 
         data_in = 8'd101; // Data to send
         wait(tx_data_ready); // Wait for the transmitter to be ready
-        #1; // Small delay to ensure the data is latched
+        
 
         tx_data_valid = 1'b1; // Indicate that the data is valid
 

Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v

@@ -39,7 +39,7 @@ module tb_uart_tx_fifo;
     );
 
     initial begin
-        $dumpfile("runs/uart_tx_fifo.vcd");
+        $dumpfile("runs/sim.vcd");
         $dumpvars(0, tb_uart_tx_fifo);
 
         $display("======== Start UART TX FIFO test =========");