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Update testbench and simulation scripts to use a unified output file name for GTKWave

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This commit is contained in:
Gamenight77
2025-05-19 09:31:53 +02:00
parent 75d1ff029b
commit 1006b77e95
5 changed files with 6 additions and 6 deletions
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2
Semaine_4/UART_FIFO/scripts/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off @echo off
echo === Lancement de GTKWave === echo === Lancement de GTKWave ===
gtkwave runs/uart_tx_fifo.vcd gtkwave runs/sim.vcd

2
Semaine_4/UART_FIFO/scripts/simulate.bat
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@@ -6,7 +6,7 @@ setlocal enabledelayedexpansion
set OUT=runs/sim.vvp set OUT=runs/sim.vvp
:: Top-level testbench module :: Top-level testbench module
set TOP=tb_uart_tx_fifo set TOP=tb_uart_rx_fifo
:: Répertoires contenant des fichiers .v :: Répertoires contenant des fichiers .v
set DIRS=src/verilog tests/verilog IP/verilog set DIRS=src/verilog tests/verilog IP/verilog

2
Semaine_4/UART_FIFO/tests/verilog/tb_uart_fifo.v
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@@ -45,7 +45,7 @@ module tb_uart_fifo;
); );
initial begin initial begin
$dumpfile("runs/uart_fifo.vcd"); $dumpfile("runs/sim.vcd");
$dumpvars(0, tb_uart_fifo); $dumpvars(0, tb_uart_fifo);
$display("======== Start UART LOOPBACK test ========="); $display("======== Start UART LOOPBACK test =========");

4
Semaine_4/UART_FIFO/tests/verilog/tb_uart_rx_fifo.v
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@@ -42,7 +42,7 @@ module tb_uart_rx_fifo;
always #(CLK_PERIOD_NS/2) clk = ~clk; always #(CLK_PERIOD_NS/2) clk = ~clk;
initial begin initial begin
$dumpfile("runs/uart_rx_fifo.vcd"); $dumpfile("runs/sim.vcd");
$dumpvars(0, tb_uart_rx_fifo); $dumpvars(0, tb_uart_rx_fifo);
$display("======== Start UART RX FIFO test ========="); $display("======== Start UART RX FIFO test =========");
#100; #100;
@@ -69,7 +69,7 @@ module tb_uart_rx_fifo;
data_in = 8'd101; // Data to send data_in = 8'd101; // Data to send
wait(tx_data_ready); // Wait for the transmitter to be ready wait(tx_data_ready); // Wait for the transmitter to be ready
#1; // Small delay to ensure the data is latched
tx_data_valid = 1'b1; // Indicate that the data is valid tx_data_valid = 1'b1; // Indicate that the data is valid

2
Semaine_4/UART_FIFO/tests/verilog/tb_uart_tx_fifo.v
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@@ -39,7 +39,7 @@ module tb_uart_tx_fifo;
); );
initial begin initial begin
$dumpfile("runs/uart_tx_fifo.vcd"); $dumpfile("runs/sim.vcd");
$dumpvars(0, tb_uart_tx_fifo); $dumpvars(0, tb_uart_tx_fifo);
$display("======== Start UART TX FIFO test ========="); $display("======== Start UART TX FIFO test =========");