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Refactor ultrasonic_fpga and ultrasonic_sensor modules for improved functionality

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- Initialized registers in ultrasonic_fpga to avoid undefined behavior.
- Modified state machine in ultrasonic_fpga to include a COMPUTE state for better echo measurement handling.
- Adjusted echo counting logic to ensure accurate distance calculation.
- Updated ultrasonic_sensor to allow for a more flexible trigger pulse timing by reducing the threshold for valid triggers.
This commit is contained in:
Gamenight77
2025-04-28 10:33:36 +02:00
parent 505f71974e
commit 1811301ef2
4 changed files with 12660 additions and 738 deletions
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720
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/sim.out
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12628
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic.vcd
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48
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_fpga.v
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@@ -7,10 +7,10 @@ module ultrasonic_fpga #(
output reg [15:0] distance, // Distance mesurée en cm
output reg [2:0] state
);
reg [15:0] trig_counter;
reg [31:0] echo_counter;
reg [31:0] echo_div_counter;
reg [15:0] distance_counter;
reg [15:0] trig_counter = 0;
reg [31:0] echo_counter = 0;
reg [31:0] echo_div_counter = 0;
reg [15:0] distance_counter = 0;
reg sig_out;
reg sig_dir; // 1: output, 0: input
@@ -24,13 +24,14 @@ module ultrasonic_fpga #(
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
DONE = 3'd5,
WAIT_NEXT = 3'd6;
COMPUTE = 3'd5,
DONE = 3'd6,
WAIT_NEXT = 3'd7;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1_000_000;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1000000;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
@@ -46,7 +47,7 @@ module ultrasonic_fpga #(
case (state)
IDLE: begin
sig_out <= 0;
sig_dir <= 1;
sig_dir <= 0;
distance <= 0;
if (start) begin
state <= TRIG_HIGH;
@@ -68,7 +69,11 @@ module ultrasonic_fpga #(
TRIG_LOW: begin
sig_out <= 0;
sig_dir <= 0; // Mettre en entrée
state <= WAIT_ECHO;
if (sig_ok) begin
state <= TRIG_LOW;
end else
state <= WAIT_ECHO;
end
WAIT_ECHO: begin
@@ -87,20 +92,21 @@ module ultrasonic_fpga #(
if (sig_ok) begin
if (echo_counter < TIMEOUT_CYCLES) begin
echo_counter <= echo_counter + 1;
end else begin
distance <= 0;
end else begin
state <= DONE;
end
end else begin //Comptage par cycle de dist diviseur
echo_counter <= echo_counter + 1;
if (echo_div_counter >= DIST_DIVISOR - 1) begin
echo_div_counter <= 0;
distance_counter <= distance_counter + 1;
end else begin
echo_div_counter <= echo_div_counter + 1;
end
end else begin
state <= COMPUTE;
end
end
COMPUTE: begin
if (echo_counter >= DIST_DIVISOR) begin
echo_counter <= echo_counter - DIST_DIVISOR;
distance_counter <= distance_counter + 1;
state <= COMPUTE;
end else begin
distance <= distance_counter;
state <= DONE;
end
@@ -121,6 +127,8 @@ module ultrasonic_fpga #(
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= TRIG_HIGH;
trig_counter <= 0;
distance_counter <= 0;
echo_counter <= 0;
end
end

2
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_sensor.v
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@@ -67,7 +67,7 @@ module ultrasonic_sensor( // Simulation of an ultrasonic sensor
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES) begin
if (trig_counter >= TRIG_PULSE_CYCLES-20) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;