forked from tanchou/Verilog
New Week
This commit is contained in:
Gamenight77
@@ -36,7 +36,7 @@ module ultrasonic_fpga #(
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reg [31:0] wait_counter;
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always @(posedge clk) begin
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always @(posedge clk) begin
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sig_int <= sig;
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sig_ok <= sig_int;
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end
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@@ -120,6 +120,7 @@ module ultrasonic_fpga #(
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wait_counter <= wait_counter + 1;
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if (wait_counter >= WAIT_NEXT_CYCLES) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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end
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end
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@@ -7,8 +7,8 @@ module ultrasonic_sensor( // Simulation of an ultrasonic sensor
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reg [2:0] state = 3'd0; // State of the FSM
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reg [2:0] next_state;
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reg sig_dir; // 1: output, 0: input
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reg [15:0] trig_counter; // Counter for the trigger pulse
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reg [31:0] echo_counter; // Echo signal
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reg [15:0] trig_counter = 0; // Counter for the trigger pulse
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reg [31:0] echo_counter = 0; // Echo signal
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reg valid_trig = 0; // Valid trigger signal
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reg echo_sended = 0; // Flag to indicate if echo has been sent
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@@ -67,7 +67,7 @@ module ultrasonic_sensor( // Simulation of an ultrasonic sensor
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if (signal == 1) begin
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trig_counter <= trig_counter + 1;
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end else begin
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if (trig_counter >= TRIG_PULSE_CYCLES-20000 && trig_counter <= TRIG_PULSE_CYCLES+20000) begin
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if (trig_counter >= TRIG_PULSE_CYCLES) begin
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valid_trig <= 1;
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end else begin
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valid_trig <= 0;
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@@ -0,0 +1,29 @@
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module distance_display_led (
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input wire [8:0] distance,
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output reg [5:0] leds
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);
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// Constante
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parameter MIN_DIST = 2;
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parameter MAX_DIST = 349;
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parameter LEVELS = 5;
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parameter PART_SIZE = (MAX_DIST - MIN_DIST + 1) / LEVELS;
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always @(*) begin
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if (distance <= MIN_DIST + PART_SIZE*0)
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leds = 6'b111111;
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else if (distance <= MIN_DIST + PART_SIZE*1)
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leds = 6'b111110;
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else if (distance <= MIN_DIST + PART_SIZE*2)
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leds = 6'b111100;
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else if (distance <= MIN_DIST + PART_SIZE*3)
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leds = 6'b111000;
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else if (distance <= MIN_DIST + PART_SIZE*4)
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leds = 6'b110000;
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else if (distance <= MIN_DIST + PART_SIZE*5)
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leds = 6'b100000;
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else
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leds = 6'b000000;
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end
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endmodule
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@@ -0,0 +1,26 @@
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module tb_distance_display_led;
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reg [8:0] distance;
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wire [5:0] leds;
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distance_display_led uut (
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.distance(distance),
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.leds(leds)
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);
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integer i;
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initial begin
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$dumpfile("distance_display_led.vcd");
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$dumpvars(0, tb_distance_display_led);
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// Test de la conversion de distance en LED
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for (i = 0; i <= 380; i = i + 10) begin
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distance = i;
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#10;
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$display("Distance: %3d cm => LEDs: %b", distance, leds);
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end
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$finish;
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end
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endmodule
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471
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/sim.out
Normal file
471
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/sim.out
Normal file
@@ -0,0 +1,471 @@
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#!
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:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 12;
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:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
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:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
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:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
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:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
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:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
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S_00000235513c4b70 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
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.timescale -9 -12;
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P_00000235513be7d0 .param/l "CLK_FREQ" 0 2 13, +C4<00000001100110111111110011000000>;
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v0000023551441c40_0 .var "clk", 0 0;
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v0000023551441d80_0 .net "distance", 15 0, v00000235513c6040_0; 1 drivers
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RS_00000235513ef028 .resolv tri, L_0000023551441380, L_0000023551442d20;
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v0000023551441ce0_0 .net8 "sig", 0 0, RS_00000235513ef028; 2 drivers
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v00000235514417e0_0 .var "start", 0 0;
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S_00000235513c4f10 .scope module, "sensor" "ultrasonic_sensor" 2 22, 3 1 0, S_00000235513c4b70;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "clk";
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.port_info 1 /INOUT 1 "signal";
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P_00000235513c2970 .param/l "CLK_FREQ" 0 3 5, +C4<00000001100110111111110011000000>;
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P_00000235513c29a8 .param/l "S_MEASURE_TRIG" 1 3 20, C4<001>;
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P_00000235513c29e0 .param/l "S_SEND_ECHO" 1 3 21, C4<010>;
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P_00000235513c2a18 .param/l "S_WAIT_TRIG" 1 3 19, C4<000>;
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P_00000235513c2a50 .param/l "TRIG_PULSE_CYCLES" 1 3 23, +C4<00000000000000000000000100001110>;
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o00000235513eef08 .functor BUFZ 1, c4<z>; HiZ drive
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; Elide local net with no drivers, v00000235513c6680_0 name=_ivl_0
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v00000235513c5d20_0 .net "clk", 0 0, v0000023551441c40_0; 1 drivers
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v00000235513c5c80_0 .var "echo_delay_counter", 15 0;
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v00000235513c6400_0 .var "echo_sended", 0 0;
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v00000235513c6720_0 .var "next_state", 2 0;
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v00000235513c5f00_0 .var "sig_dir", 0 0;
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v00000235513c69a0_0 .net8 "signal", 0 0, RS_00000235513ef028; alias, 2 drivers
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v00000235513c65e0_0 .var "signal_out", 0 0;
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v00000235513c60e0_0 .var "state", 2 0;
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v00000235513c6a40_0 .var "trig_counter", 15 0;
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v00000235513c67c0_0 .var "valid_trig", 0 0;
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E_00000235513bfb50 .event posedge, v00000235513c5d20_0;
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E_00000235513bf790 .event anyedge, v00000235513c60e0_0, v00000235513c69a0_0, v00000235513c67c0_0, v00000235513c6400_0;
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L_0000023551442d20 .functor MUXZ 1, o00000235513eef08, v00000235513c65e0_0, v00000235513c5f00_0, C4<>;
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S_00000235512ada20 .scope module, "uut" "ultrasonic_fpga" 2 15, 4 1 0, S_00000235513c4b70;
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.timescale -9 -12;
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.port_info 0 /INPUT 1 "clk";
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.port_info 1 /INPUT 1 "start";
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.port_info 2 /INOUT 1 "sig";
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.port_info 3 /OUTPUT 16 "distance";
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.port_info 4 /OUTPUT 3 "state";
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P_00000235512adbb0 .param/l "CLK_FREQ" 0 4 2, +C4<00000001100110111111110011000000>;
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P_00000235512adbe8 .param/l "DIST_DIVISOR" 1 4 31, +C4<00000000000000000000011000011110>;
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P_00000235512adc20 .param/l "DONE" 1 4 27, C4<101>;
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P_00000235512adc58 .param/l "IDLE" 1 4 22, C4<000>;
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P_00000235512adc90 .param/l "MAX_CM" 1 4 32, +C4<00000000000000000000000101011110>;
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P_00000235512adcc8 .param/l "MEASURE_ECHO" 1 4 26, C4<100>;
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P_00000235512add00 .param/l "TIMEOUT_CYCLES" 1 4 33, +C4<11111111111111111111100110001001>;
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P_00000235512add38 .param/l "TRIG_HIGH" 1 4 23, C4<001>;
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P_00000235512add70 .param/l "TRIG_LOW" 1 4 24, C4<010>;
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P_00000235512adda8 .param/l "TRIG_PULSE_CYCLES" 1 4 30, +C4<00000000000000000000000100001110>;
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P_00000235512adde0 .param/l "WAIT_ECHO" 1 4 25, C4<011>;
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P_00000235512ade18 .param/l "WAIT_NEXT" 1 4 28, C4<110>;
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P_00000235512ade50 .param/l "WAIT_NEXT_CYCLES" 1 4 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>;
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o00000235513ef178 .functor BUFZ 1, c4<z>; HiZ drive
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; Elide local net with no drivers, v00000235513c6360_0 name=_ivl_0
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v00000235513c5e60_0 .net "clk", 0 0, v0000023551441c40_0; alias, 1 drivers
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v00000235513c6040_0 .var "distance", 15 0;
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v00000235513c5fa0_0 .var "distance_counter", 15 0;
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v00000235513c6860_0 .var "echo_counter", 31 0;
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v00000235513c64a0_0 .var "echo_div_counter", 31 0;
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v00000235513c6540_0 .net8 "sig", 0 0, RS_00000235513ef028; alias, 2 drivers
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v00000235513c6900_0 .var "sig_dir", 0 0;
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v00000235513c5b40_0 .var "sig_int", 0 0;
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v00000235513c5be0_0 .var "sig_ok", 0 0;
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v00000235513c5dc0_0 .var "sig_out", 0 0;
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v00000235513c6180_0 .net "start", 0 0, v00000235514417e0_0; 1 drivers
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v00000235513c6220_0 .var "state", 2 0;
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v00000235513c62c0_0 .var "trig_counter", 15 0;
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v00000235514414c0_0 .var "wait_counter", 31 0;
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L_0000023551441380 .functor MUXZ 1, o00000235513ef178, v00000235513c5dc0_0, v00000235513c6900_0, C4<>;
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.scope S_00000235512ada20;
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T_0 ;
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%wait E_00000235513bfb50;
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%load/vec4 v00000235513c6540_0;
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%assign/vec4 v00000235513c5b40_0, 0;
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%load/vec4 v00000235513c5b40_0;
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%assign/vec4 v00000235513c5be0_0, 0;
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%jmp T_0;
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.thread T_0;
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.scope S_00000235512ada20;
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T_1 ;
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%wait E_00000235513bfb50;
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%load/vec4 v00000235513c6220_0;
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%dup/vec4;
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%pushi/vec4 0, 0, 3;
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%cmp/u;
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%jmp/1 T_1.0, 6;
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%dup/vec4;
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%pushi/vec4 1, 0, 3;
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%cmp/u;
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%jmp/1 T_1.1, 6;
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%dup/vec4;
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%pushi/vec4 2, 0, 3;
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%cmp/u;
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%jmp/1 T_1.2, 6;
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%dup/vec4;
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%pushi/vec4 3, 0, 3;
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%cmp/u;
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%jmp/1 T_1.3, 6;
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%dup/vec4;
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%pushi/vec4 4, 0, 3;
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%cmp/u;
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%jmp/1 T_1.4, 6;
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%dup/vec4;
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%pushi/vec4 5, 0, 3;
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%cmp/u;
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%jmp/1 T_1.5, 6;
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%dup/vec4;
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%pushi/vec4 6, 0, 3;
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%cmp/u;
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%jmp/1 T_1.6, 6;
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%pushi/vec4 0, 0, 3;
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%assign/vec4 v00000235513c6220_0, 0;
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%jmp T_1.8;
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T_1.0 ;
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%pushi/vec4 0, 0, 1;
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%assign/vec4 v00000235513c5dc0_0, 0;
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%pushi/vec4 1, 0, 1;
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%assign/vec4 v00000235513c6900_0, 0;
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%pushi/vec4 0, 0, 16;
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%assign/vec4 v00000235513c6040_0, 0;
|
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%load/vec4 v00000235513c6180_0;
|
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%flag_set/vec4 8;
|
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%jmp/0xz T_1.9, 8;
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%pushi/vec4 1, 0, 3;
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%assign/vec4 v00000235513c6220_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000235513c62c0_0, 0;
|
||||
T_1.9 ;
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%jmp T_1.8;
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T_1.1 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000235513c5dc0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000235513c6900_0, 0;
|
||||
%load/vec4 v00000235513c62c0_0;
|
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%pad/u 32;
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%cmpi/u 270, 0, 32;
|
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%jmp/0xz T_1.11, 5;
|
||||
%load/vec4 v00000235513c62c0_0;
|
||||
%addi 1, 0, 16;
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||||
%assign/vec4 v00000235513c62c0_0, 0;
|
||||
%jmp T_1.12;
|
||||
T_1.11 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000235513c62c0_0, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
T_1.12 ;
|
||||
%jmp T_1.8;
|
||||
T_1.2 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000235513c5dc0_0, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000235513c6900_0, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
%jmp T_1.8;
|
||||
T_1.3 ;
|
||||
%load/vec4 v00000235513c5be0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.13, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000235513c6860_0, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
%jmp T_1.14;
|
||||
T_1.13 ;
|
||||
%load/vec4 v00000235513c6860_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.15, 5;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000235513c6040_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
%jmp T_1.16;
|
||||
T_1.15 ;
|
||||
%load/vec4 v00000235513c6860_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000235513c6860_0, 0;
|
||||
T_1.16 ;
|
||||
T_1.14 ;
|
||||
%jmp T_1.8;
|
||||
T_1.4 ;
|
||||
%load/vec4 v00000235513c5be0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.17, 8;
|
||||
%load/vec4 v00000235513c6860_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%jmp/0xz T_1.19, 5;
|
||||
%load/vec4 v00000235513c6860_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000235513c6860_0, 0;
|
||||
%jmp T_1.20;
|
||||
T_1.19 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000235513c6040_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
T_1.20 ;
|
||||
%jmp T_1.18;
|
||||
T_1.17 ;
|
||||
%load/vec4 v00000235513c6860_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000235513c6860_0, 0;
|
||||
%load/vec4 v00000235513c64a0_0;
|
||||
%cmpi/u 1565, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.21, 5;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000235513c64a0_0, 0;
|
||||
%load/vec4 v00000235513c5fa0_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000235513c5fa0_0, 0;
|
||||
%jmp T_1.22;
|
||||
T_1.21 ;
|
||||
%load/vec4 v00000235513c64a0_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000235513c64a0_0, 0;
|
||||
T_1.22 ;
|
||||
%load/vec4 v00000235513c5fa0_0;
|
||||
%assign/vec4 v00000235513c6040_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
T_1.18 ;
|
||||
%jmp T_1.8;
|
||||
T_1.5 ;
|
||||
%load/vec4 v00000235513c6180_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.23, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000235514414c0_0, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
%jmp T_1.24;
|
||||
T_1.23 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
T_1.24 ;
|
||||
%jmp T_1.8;
|
||||
T_1.6 ;
|
||||
%load/vec4 v00000235514414c0_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000235514414c0_0, 0;
|
||||
%load/vec4 v00000235514414c0_0;
|
||||
%pad/u 64;
|
||||
%cmpi/u 2700000, 0, 64;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.25, 5;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v00000235513c6220_0, 0;
|
||||
T_1.25 ;
|
||||
%jmp T_1.8;
|
||||
T_1.8 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_00000235513c4f10;
|
||||
T_2 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000235513c60e0_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c67c0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c6400_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c65e0_0, 0, 1;
|
||||
%end;
|
||||
.thread T_2;
|
||||
.scope S_00000235513c4f10;
|
||||
T_3 ;
|
||||
%wait E_00000235513bf790;
|
||||
%load/vec4 v00000235513c60e0_0;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.0, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.1, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.2, 6;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c5f00_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
%jmp T_3.4;
|
||||
T_3.0 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c5f00_0, 0, 1;
|
||||
%load/vec4 v00000235513c69a0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_3.5, 4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
%jmp T_3.6;
|
||||
T_3.5 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
T_3.6 ;
|
||||
%jmp T_3.4;
|
||||
T_3.1 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c5f00_0, 0, 1;
|
||||
%load/vec4 v00000235513c67c0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.7, 8;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
T_3.7 ;
|
||||
%jmp T_3.4;
|
||||
T_3.2 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000235513c5f00_0, 0, 1;
|
||||
%load/vec4 v00000235513c6400_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.9, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235513c6400_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
%jmp T_3.10;
|
||||
T_3.9 ;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000235513c6720_0, 0, 3;
|
||||
T_3.10 ;
|
||||
%jmp T_3.4;
|
||||
T_3.4 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_3;
|
||||
.thread T_3, $push;
|
||||
.scope S_00000235513c4f10;
|
||||
T_4 ;
|
||||
%wait E_00000235513bfb50;
|
||||
%load/vec4 v00000235513c6720_0;
|
||||
%assign/vec4 v00000235513c60e0_0, 0;
|
||||
%jmp T_4;
|
||||
.thread T_4;
|
||||
.scope S_00000235513c4f10;
|
||||
T_5 ;
|
||||
%wait E_00000235513bfb50;
|
||||
%load/vec4 v00000235513c60e0_0;
|
||||
%cmpi/e 1, 0, 3;
|
||||
%jmp/0xz T_5.0, 4;
|
||||
%load/vec4 v00000235513c69a0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_5.2, 4;
|
||||
%load/vec4 v00000235513c6a40_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000235513c6a40_0, 0;
|
||||
%jmp T_5.3;
|
||||
T_5.2 ;
|
||||
%load/vec4 v00000235513c6a40_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 4294947566, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%flag_get/vec4 5;
|
||||
%jmp/0 T_5.6, 5;
|
||||
%load/vec4 v00000235513c6a40_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 20270, 0, 32;
|
||||
%flag_get/vec4 4;
|
||||
%flag_get/vec4 5;
|
||||
%or;
|
||||
%and;
|
||||
T_5.6;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_5.4, 8;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000235513c67c0_0, 0;
|
||||
%jmp T_5.5;
|
||||
T_5.4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000235513c67c0_0, 0;
|
||||
T_5.5 ;
|
||||
T_5.3 ;
|
||||
T_5.0 ;
|
||||
%jmp T_5;
|
||||
.thread T_5;
|
||||
.scope S_00000235513c4f10;
|
||||
T_6 ;
|
||||
%wait E_00000235513bfb50;
|
||||
%load/vec4 v00000235513c60e0_0;
|
||||
%cmpi/e 2, 0, 3;
|
||||
%jmp/0xz T_6.0, 4;
|
||||
%load/vec4 v00000235513c5c80_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 5800, 0, 32;
|
||||
%jmp/0xz T_6.2, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000235513c65e0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000235513c6400_0, 0;
|
||||
%jmp T_6.3;
|
||||
T_6.2 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000235513c65e0_0, 0;
|
||||
%load/vec4 v00000235513c5c80_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000235513c5c80_0, 0;
|
||||
T_6.3 ;
|
||||
%jmp T_6.1;
|
||||
T_6.0 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000235513c5c80_0, 0;
|
||||
T_6.1 ;
|
||||
%jmp T_6;
|
||||
.thread T_6;
|
||||
.scope S_00000235513c4b70;
|
||||
T_7 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000023551441c40_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235514417e0_0, 0, 1;
|
||||
%end;
|
||||
.thread T_7;
|
||||
.scope S_00000235513c4b70;
|
||||
T_8 ;
|
||||
%delay 18000, 0;
|
||||
%load/vec4 v0000023551441c40_0;
|
||||
%inv;
|
||||
%store/vec4 v0000023551441c40_0, 0, 1;
|
||||
%jmp T_8;
|
||||
.thread T_8;
|
||||
.scope S_00000235513c4b70;
|
||||
T_9 ;
|
||||
%vpi_call 2 28 "$dumpfile", "ultrasonic.vcd" {0 0 0};
|
||||
%vpi_call 2 29 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000235513c4b70 {0 0 0};
|
||||
%delay 100000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000235514417e0_0, 0, 1;
|
||||
%delay 40000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000235514417e0_0, 0, 1;
|
||||
%delay 600000000, 0;
|
||||
%vpi_call 2 40 "$display", "Distance mesur\303\251e: %d cm", v0000023551441d80_0 {0 0 0};
|
||||
%load/vec4 v0000023551441d80_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 0, 0, 32;
|
||||
%flag_or 5, 4; GT is !LE
|
||||
%flag_inv 5;
|
||||
%jmp/0xz T_9.0, 5;
|
||||
%vpi_call 2 45 "$display", "Distance measured: %d cm", v0000023551441d80_0 {0 0 0};
|
||||
%jmp T_9.1;
|
||||
T_9.0 ;
|
||||
%vpi_call 2 47 "$display", "No distance measured." {0 0 0};
|
||||
T_9.1 ;
|
||||
%vpi_call 2 50 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_9;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 5;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb_ultrasonic_fpga.v";
|
||||
"ultrasonic_sensor.v";
|
||||
"ultrasonic_fpga.v";
|
||||
@@ -0,0 +1,53 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_ultrasonic_fpga;
|
||||
|
||||
reg clk = 0;
|
||||
reg start = 0;
|
||||
wire sig;
|
||||
wire [15:0] distance;
|
||||
|
||||
// Clock 27MHz => periode = 37ns
|
||||
always #18 clk = ~clk;
|
||||
|
||||
parameter CLK_FREQ = 27_000_000; // 27 MHz
|
||||
|
||||
ultrasonic_fpga uut (
|
||||
.clk(clk),
|
||||
.start(start),
|
||||
.sig(sig),
|
||||
.distance(distance)
|
||||
);
|
||||
|
||||
ultrasonic_sensor sensor (
|
||||
.clk(clk),
|
||||
.signal(sig)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("ultrasonic.vcd");
|
||||
$dumpvars(0, tb_ultrasonic_fpga);
|
||||
|
||||
// Start
|
||||
#100;
|
||||
start = 1;
|
||||
#40;
|
||||
start = 0;
|
||||
|
||||
// Attendre que la distance soit mesurée
|
||||
// wait (distance > 0);
|
||||
#600000; // petite marge pour stabiliser
|
||||
$display("Distance mesurée: %d cm", distance);
|
||||
|
||||
|
||||
// Affiche la distance
|
||||
if (distance > 0) begin
|
||||
$display("Distance measured: %d cm", distance);
|
||||
end else begin
|
||||
$display("No distance measured.");
|
||||
end
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,471 @@
|
||||
#!
|
||||
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 12;
|
||||
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\va_math.vpi";
|
||||
S_000001b750674ff0 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
|
||||
.timescale -9 -12;
|
||||
P_000001b75066f080 .param/l "CLK_FREQ" 0 2 13, +C4<00000001100110111111110011000000>;
|
||||
v000001b7506ef330_0 .var "clk", 0 0;
|
||||
v000001b7506ef970_0 .net "distance", 15 0, v000001b7506ef5b0_0; 1 drivers
|
||||
RS_000001b75069f0b8 .resolv tri, L_000001b7506efc90, L_000001b7506f1530;
|
||||
v000001b7506ef470_0 .net8 "sig", 0 0, RS_000001b75069f0b8; 2 drivers
|
||||
v000001b7506ef650_0 .var "start", 0 0;
|
||||
S_000001b750675390 .scope module, "sensor" "ultrasonic_sensor" 2 22, 3 1 0, S_000001b750674ff0;
|
||||
.timescale -9 -12;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INOUT 1 "signal";
|
||||
P_000001b750672df0 .param/l "CLK_FREQ" 0 3 5, +C4<00000001100110111111110011000000>;
|
||||
P_000001b750672e28 .param/l "S_MEASURE_TRIG" 1 3 20, C4<001>;
|
||||
P_000001b750672e60 .param/l "S_SEND_ECHO" 1 3 21, C4<010>;
|
||||
P_000001b750672e98 .param/l "S_WAIT_TRIG" 1 3 19, C4<000>;
|
||||
P_000001b750672ed0 .param/l "TRIG_PULSE_CYCLES" 1 3 23, +C4<00000000000000000000000100001110>;
|
||||
o000001b75069ef98 .functor BUFZ 1, c4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v000001b75074a970_0 name=_ivl_0
|
||||
v000001b75074ae10_0 .net "clk", 0 0, v000001b7506ef330_0; 1 drivers
|
||||
v000001b75074af30_0 .var "echo_delay_counter", 15 0;
|
||||
v000001b75068feb0_0 .var "echo_sended", 0 0;
|
||||
v000001b750675520_0 .var "next_state", 2 0;
|
||||
v000001b7506755c0_0 .var "sig_dir", 0 0;
|
||||
v000001b7506effb0_0 .net8 "signal", 0 0, RS_000001b75069f0b8; alias, 2 drivers
|
||||
v000001b7506ef830_0 .var "signal_out", 0 0;
|
||||
v000001b7506ef510_0 .var "state", 2 0;
|
||||
v000001b7506ef0b0_0 .var "trig_counter", 15 0;
|
||||
v000001b7506efdd0_0 .var "valid_trig", 0 0;
|
||||
E_000001b750670380 .event posedge, v000001b75074ae10_0;
|
||||
E_000001b75066fac0 .event anyedge, v000001b7506ef510_0, v000001b7506effb0_0, v000001b7506efdd0_0, v000001b75068feb0_0;
|
||||
L_000001b7506f1530 .functor MUXZ 1, o000001b75069ef98, v000001b7506ef830_0, v000001b7506755c0_0, C4<>;
|
||||
S_000001b75074d480 .scope module, "uut" "ultrasonic_fpga" 2 15, 4 1 0, S_000001b750674ff0;
|
||||
.timescale -9 -12;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "start";
|
||||
.port_info 2 /INOUT 1 "sig";
|
||||
.port_info 3 /OUTPUT 16 "distance";
|
||||
.port_info 4 /OUTPUT 3 "state";
|
||||
P_000001b75074d610 .param/l "CLK_FREQ" 0 4 2, +C4<00000001100110111111110011000000>;
|
||||
P_000001b75074d648 .param/l "DIST_DIVISOR" 1 4 31, +C4<00000000000000000000011000011110>;
|
||||
P_000001b75074d680 .param/l "DONE" 1 4 27, C4<101>;
|
||||
P_000001b75074d6b8 .param/l "IDLE" 1 4 22, C4<000>;
|
||||
P_000001b75074d6f0 .param/l "MAX_CM" 1 4 32, +C4<00000000000000000000000101011110>;
|
||||
P_000001b75074d728 .param/l "MEASURE_ECHO" 1 4 26, C4<100>;
|
||||
P_000001b75074d760 .param/l "TIMEOUT_CYCLES" 1 4 33, +C4<11111111111111111111100110001001>;
|
||||
P_000001b75074d798 .param/l "TRIG_HIGH" 1 4 23, C4<001>;
|
||||
P_000001b75074d7d0 .param/l "TRIG_LOW" 1 4 24, C4<010>;
|
||||
P_000001b75074d808 .param/l "TRIG_PULSE_CYCLES" 1 4 30, +C4<00000000000000000000000100001110>;
|
||||
P_000001b75074d840 .param/l "WAIT_ECHO" 1 4 25, C4<011>;
|
||||
P_000001b75074d878 .param/l "WAIT_NEXT" 1 4 28, C4<110>;
|
||||
P_000001b75074d8b0 .param/l "WAIT_NEXT_CYCLES" 1 4 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>;
|
||||
o000001b75069f208 .functor BUFZ 1, c4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v000001b7506ef150_0 name=_ivl_0
|
||||
v000001b7506efa10_0 .net "clk", 0 0, v000001b7506ef330_0; alias, 1 drivers
|
||||
v000001b7506ef5b0_0 .var "distance", 15 0;
|
||||
v000001b7506ef6f0_0 .var "distance_counter", 15 0;
|
||||
v000001b7506eff10_0 .var "echo_counter", 31 0;
|
||||
v000001b7506efbf0_0 .var "echo_div_counter", 31 0;
|
||||
v000001b7506ef790_0 .net8 "sig", 0 0, RS_000001b75069f0b8; alias, 2 drivers
|
||||
v000001b7506ef1f0_0 .var "sig_dir", 0 0;
|
||||
v000001b7506ef3d0_0 .var "sig_int", 0 0;
|
||||
v000001b7506efd30_0 .var "sig_ok", 0 0;
|
||||
v000001b7506ef8d0_0 .var "sig_out", 0 0;
|
||||
v000001b7506efab0_0 .net "start", 0 0, v000001b7506ef650_0; 1 drivers
|
||||
v000001b7506ef290_0 .var "state", 2 0;
|
||||
v000001b7506efe70_0 .var "trig_counter", 15 0;
|
||||
v000001b7506efb50_0 .var "wait_counter", 31 0;
|
||||
L_000001b7506efc90 .functor MUXZ 1, o000001b75069f208, v000001b7506ef8d0_0, v000001b7506ef1f0_0, C4<>;
|
||||
.scope S_000001b75074d480;
|
||||
T_0 ;
|
||||
%wait E_000001b750670380;
|
||||
%load/vec4 v000001b7506ef790_0;
|
||||
%assign/vec4 v000001b7506ef3d0_0, 0;
|
||||
%load/vec4 v000001b7506ef3d0_0;
|
||||
%assign/vec4 v000001b7506efd30_0, 0;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_000001b75074d480;
|
||||
T_1 ;
|
||||
%wait E_000001b750670380;
|
||||
%load/vec4 v000001b7506ef290_0;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.0, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.1, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.2, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.3, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.4, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.5, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.6, 6;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%jmp T_1.8;
|
||||
T_1.0 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001b7506ef8d0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b7506ef1f0_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b7506ef5b0_0, 0;
|
||||
%load/vec4 v000001b7506efab0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.9, 8;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b7506efe70_0, 0;
|
||||
T_1.9 ;
|
||||
%jmp T_1.8;
|
||||
T_1.1 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b7506ef8d0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b7506ef1f0_0, 0;
|
||||
%load/vec4 v000001b7506efe70_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 270, 0, 32;
|
||||
%jmp/0xz T_1.11, 5;
|
||||
%load/vec4 v000001b7506efe70_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v000001b7506efe70_0, 0;
|
||||
%jmp T_1.12;
|
||||
T_1.11 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b7506efe70_0, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
T_1.12 ;
|
||||
%jmp T_1.8;
|
||||
T_1.2 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001b7506ef8d0_0, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001b7506ef1f0_0, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%jmp T_1.8;
|
||||
T_1.3 ;
|
||||
%load/vec4 v000001b7506efd30_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.13, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v000001b7506eff10_0, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%jmp T_1.14;
|
||||
T_1.13 ;
|
||||
%load/vec4 v000001b7506eff10_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.15, 5;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b7506ef5b0_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%jmp T_1.16;
|
||||
T_1.15 ;
|
||||
%load/vec4 v000001b7506eff10_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v000001b7506eff10_0, 0;
|
||||
T_1.16 ;
|
||||
T_1.14 ;
|
||||
%jmp T_1.8;
|
||||
T_1.4 ;
|
||||
%load/vec4 v000001b7506efd30_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.17, 8;
|
||||
%load/vec4 v000001b7506eff10_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%jmp/0xz T_1.19, 5;
|
||||
%load/vec4 v000001b7506eff10_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v000001b7506eff10_0, 0;
|
||||
%jmp T_1.20;
|
||||
T_1.19 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b7506ef5b0_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
T_1.20 ;
|
||||
%jmp T_1.18;
|
||||
T_1.17 ;
|
||||
%load/vec4 v000001b7506eff10_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v000001b7506eff10_0, 0;
|
||||
%load/vec4 v000001b7506efbf0_0;
|
||||
%cmpi/u 1565, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.21, 5;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v000001b7506efbf0_0, 0;
|
||||
%load/vec4 v000001b7506ef6f0_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v000001b7506ef6f0_0, 0;
|
||||
%jmp T_1.22;
|
||||
T_1.21 ;
|
||||
%load/vec4 v000001b7506efbf0_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v000001b7506efbf0_0, 0;
|
||||
T_1.22 ;
|
||||
%load/vec4 v000001b7506ef6f0_0;
|
||||
%assign/vec4 v000001b7506ef5b0_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
T_1.18 ;
|
||||
%jmp T_1.8;
|
||||
T_1.5 ;
|
||||
%load/vec4 v000001b7506efab0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.23, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v000001b7506efb50_0, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
%jmp T_1.24;
|
||||
T_1.23 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
T_1.24 ;
|
||||
%jmp T_1.8;
|
||||
T_1.6 ;
|
||||
%load/vec4 v000001b7506efb50_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v000001b7506efb50_0, 0;
|
||||
%load/vec4 v000001b7506efb50_0;
|
||||
%pad/u 64;
|
||||
%cmpi/u 2700000, 0, 64;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.25, 5;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v000001b7506ef290_0, 0;
|
||||
T_1.25 ;
|
||||
%jmp T_1.8;
|
||||
T_1.8 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_000001b750675390;
|
||||
T_2 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001b7506ef510_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506efdd0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b75068feb0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506ef830_0, 0, 1;
|
||||
%end;
|
||||
.thread T_2;
|
||||
.scope S_000001b750675390;
|
||||
T_3 ;
|
||||
%wait E_000001b75066fac0;
|
||||
%load/vec4 v000001b7506ef510_0;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.0, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.1, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_3.2, 6;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506755c0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
%jmp T_3.4;
|
||||
T_3.0 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506755c0_0, 0, 1;
|
||||
%load/vec4 v000001b7506effb0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_3.5, 4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
%jmp T_3.6;
|
||||
T_3.5 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
T_3.6 ;
|
||||
%jmp T_3.4;
|
||||
T_3.1 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506755c0_0, 0, 1;
|
||||
%load/vec4 v000001b7506efdd0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.7, 8;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
T_3.7 ;
|
||||
%jmp T_3.4;
|
||||
T_3.2 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b7506755c0_0, 0, 1;
|
||||
%load/vec4 v000001b75068feb0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.9, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b75068feb0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
%jmp T_3.10;
|
||||
T_3.9 ;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001b750675520_0, 0, 3;
|
||||
T_3.10 ;
|
||||
%jmp T_3.4;
|
||||
T_3.4 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_3;
|
||||
.thread T_3, $push;
|
||||
.scope S_000001b750675390;
|
||||
T_4 ;
|
||||
%wait E_000001b750670380;
|
||||
%load/vec4 v000001b750675520_0;
|
||||
%assign/vec4 v000001b7506ef510_0, 0;
|
||||
%jmp T_4;
|
||||
.thread T_4;
|
||||
.scope S_000001b750675390;
|
||||
T_5 ;
|
||||
%wait E_000001b750670380;
|
||||
%load/vec4 v000001b7506ef510_0;
|
||||
%cmpi/e 1, 0, 3;
|
||||
%jmp/0xz T_5.0, 4;
|
||||
%load/vec4 v000001b7506effb0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_5.2, 4;
|
||||
%load/vec4 v000001b7506ef0b0_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v000001b7506ef0b0_0, 0;
|
||||
%jmp T_5.3;
|
||||
T_5.2 ;
|
||||
%load/vec4 v000001b7506ef0b0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 4294947566, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%flag_get/vec4 5;
|
||||
%jmp/0 T_5.6, 5;
|
||||
%load/vec4 v000001b7506ef0b0_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 20270, 0, 32;
|
||||
%flag_get/vec4 4;
|
||||
%flag_get/vec4 5;
|
||||
%or;
|
||||
%and;
|
||||
T_5.6;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_5.4, 8;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b7506efdd0_0, 0;
|
||||
%jmp T_5.5;
|
||||
T_5.4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001b7506efdd0_0, 0;
|
||||
T_5.5 ;
|
||||
T_5.3 ;
|
||||
T_5.0 ;
|
||||
%jmp T_5;
|
||||
.thread T_5;
|
||||
.scope S_000001b750675390;
|
||||
T_6 ;
|
||||
%wait E_000001b750670380;
|
||||
%load/vec4 v000001b7506ef510_0;
|
||||
%cmpi/e 2, 0, 3;
|
||||
%jmp/0xz T_6.0, 4;
|
||||
%load/vec4 v000001b75074af30_0;
|
||||
%pad/u 32;
|
||||
%cmpi/e 5800, 0, 32;
|
||||
%jmp/0xz T_6.2, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001b7506ef830_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b75068feb0_0, 0;
|
||||
%jmp T_6.3;
|
||||
T_6.2 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v000001b7506ef830_0, 0;
|
||||
%load/vec4 v000001b75074af30_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v000001b75074af30_0, 0;
|
||||
T_6.3 ;
|
||||
%jmp T_6.1;
|
||||
T_6.0 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v000001b75074af30_0, 0;
|
||||
T_6.1 ;
|
||||
%jmp T_6;
|
||||
.thread T_6;
|
||||
.scope S_000001b750674ff0;
|
||||
T_7 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506ef330_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506ef650_0, 0, 1;
|
||||
%end;
|
||||
.thread T_7;
|
||||
.scope S_000001b750674ff0;
|
||||
T_8 ;
|
||||
%delay 18000, 0;
|
||||
%load/vec4 v000001b7506ef330_0;
|
||||
%inv;
|
||||
%store/vec4 v000001b7506ef330_0, 0, 1;
|
||||
%jmp T_8;
|
||||
.thread T_8;
|
||||
.scope S_000001b750674ff0;
|
||||
T_9 ;
|
||||
%vpi_call 2 28 "$dumpfile", "ultrasonic.vcd" {0 0 0};
|
||||
%vpi_call 2 29 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001b750674ff0 {0 0 0};
|
||||
%delay 100000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b7506ef650_0, 0, 1;
|
||||
%delay 40000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b7506ef650_0, 0, 1;
|
||||
%delay 600000000, 0;
|
||||
%vpi_call 2 40 "$display", "Distance mesur\303\251e: %d cm", v000001b7506ef970_0 {0 0 0};
|
||||
%load/vec4 v000001b7506ef970_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 0, 0, 32;
|
||||
%flag_or 5, 4; GT is !LE
|
||||
%flag_inv 5;
|
||||
%jmp/0xz T_9.0, 5;
|
||||
%vpi_call 2 45 "$display", "Distance measured: %d cm", v000001b7506ef970_0 {0 0 0};
|
||||
%jmp T_9.1;
|
||||
T_9.0 ;
|
||||
%vpi_call 2 47 "$display", "No distance measured." {0 0 0};
|
||||
T_9.1 ;
|
||||
%vpi_call 2 50 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_9;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 5;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb_ultrasonic_fpga.v";
|
||||
"ultrasonic_sensor.v";
|
||||
"ultrasonic_fpga.v";
|
||||
67107
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic.vcd
Normal file
67107
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic.vcd
Normal file
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,134 @@
|
||||
module ultrasonic_fpga #(
|
||||
parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
|
||||
)(
|
||||
input wire clk,
|
||||
input wire start,
|
||||
inout wire sig, // Broche bidirectionnelle vers le capteur
|
||||
output reg [15:0] distance, // Distance mesurée en cm
|
||||
output reg [2:0] state
|
||||
);
|
||||
reg [15:0] trig_counter;
|
||||
reg [31:0] echo_counter;
|
||||
reg [31:0] echo_div_counter;
|
||||
reg [15:0] distance_counter;
|
||||
|
||||
reg sig_out;
|
||||
reg sig_dir; // 1: output, 0: input
|
||||
|
||||
assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
|
||||
|
||||
reg sig_int, sig_ok;
|
||||
|
||||
localparam IDLE = 3'd0,
|
||||
TRIG_HIGH = 3'd1,
|
||||
TRIG_LOW = 3'd2,
|
||||
WAIT_ECHO = 3'd3,
|
||||
MEASURE_ECHO = 3'd4,
|
||||
DONE = 3'd5,
|
||||
WAIT_NEXT = 3'd6;
|
||||
|
||||
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
|
||||
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
|
||||
localparam integer MAX_CM = 350;
|
||||
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1_000_000;
|
||||
|
||||
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
|
||||
|
||||
reg [31:0] wait_counter;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sig_int <= sig;
|
||||
sig_ok <= sig_int;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin // FSM
|
||||
|
||||
case (state)
|
||||
IDLE: begin
|
||||
sig_out <= 0;
|
||||
sig_dir <= 1;
|
||||
distance <= 0;
|
||||
if (start) begin
|
||||
state <= TRIG_HIGH;
|
||||
trig_counter <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
TRIG_HIGH: begin
|
||||
sig_out <= 1;
|
||||
sig_dir <= 1;
|
||||
if (trig_counter < TRIG_PULSE_CYCLES) begin
|
||||
trig_counter <= trig_counter + 1;
|
||||
end else begin
|
||||
trig_counter <= 0;
|
||||
state <= TRIG_LOW;
|
||||
end
|
||||
end
|
||||
|
||||
TRIG_LOW: begin
|
||||
sig_out <= 0;
|
||||
sig_dir <= 0; // Mettre en entrée
|
||||
state <= WAIT_ECHO;
|
||||
end
|
||||
|
||||
WAIT_ECHO: begin
|
||||
if (sig_ok) begin
|
||||
echo_counter <= 0;
|
||||
state <= MEASURE_ECHO;
|
||||
end else if (echo_counter >= TIMEOUT_CYCLES) begin
|
||||
distance <= 0;
|
||||
state <= DONE;
|
||||
end else begin
|
||||
echo_counter <= echo_counter + 1;
|
||||
end
|
||||
end
|
||||
|
||||
MEASURE_ECHO: begin
|
||||
if (sig_ok) begin
|
||||
if (echo_counter < TIMEOUT_CYCLES) begin
|
||||
echo_counter <= echo_counter + 1;
|
||||
end else begin
|
||||
distance <= 0;
|
||||
state <= DONE;
|
||||
end
|
||||
end else begin //Comptage par cycle de dist diviseur
|
||||
echo_counter <= echo_counter + 1;
|
||||
|
||||
if (echo_div_counter >= DIST_DIVISOR - 1) begin
|
||||
echo_div_counter <= 0;
|
||||
distance_counter <= distance_counter + 1;
|
||||
end else begin
|
||||
echo_div_counter <= echo_div_counter + 1;
|
||||
end
|
||||
|
||||
distance <= distance_counter;
|
||||
state <= DONE;
|
||||
end
|
||||
end
|
||||
|
||||
DONE: begin
|
||||
if (start) begin
|
||||
wait_counter <= 0;
|
||||
state <= WAIT_NEXT;
|
||||
end else begin
|
||||
state <= IDLE;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
WAIT_NEXT: begin
|
||||
wait_counter <= wait_counter + 1;
|
||||
if (wait_counter >= WAIT_NEXT_CYCLES) begin
|
||||
state <= TRIG_HIGH;
|
||||
trig_counter <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
state <= IDLE; // Reset to IDLE state in case of an error
|
||||
end
|
||||
endcase
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,95 @@
|
||||
module ultrasonic_sensor( // Simulation of an ultrasonic sensor
|
||||
input wire clk,
|
||||
inout wire signal // Signal from the ultrasonic sensor
|
||||
);
|
||||
parameter integer CLK_FREQ = 27_000_000;
|
||||
|
||||
reg [2:0] state = 3'd0; // State of the FSM
|
||||
reg [2:0] next_state;
|
||||
reg sig_dir; // 1: output, 0: input
|
||||
reg [15:0] trig_counter = 0; // Counter for the trigger pulse
|
||||
reg [31:0] echo_counter = 0; // Echo signal
|
||||
reg valid_trig = 0; // Valid trigger signal
|
||||
|
||||
reg echo_sended = 0; // Flag to indicate if echo has been sent
|
||||
|
||||
reg signal_out = 0;
|
||||
assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
|
||||
|
||||
localparam S_WAIT_TRIG = 3'd0,
|
||||
S_MEASURE_TRIG = 3'd1,
|
||||
S_SEND_ECHO = 3'd2;
|
||||
|
||||
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
|
||||
|
||||
always @(*) begin
|
||||
case (state)
|
||||
S_WAIT_TRIG: begin
|
||||
sig_dir = 0;
|
||||
if (signal == 1) begin
|
||||
next_state = S_MEASURE_TRIG;
|
||||
end else begin
|
||||
next_state = S_WAIT_TRIG;
|
||||
end
|
||||
end
|
||||
|
||||
S_MEASURE_TRIG: begin
|
||||
sig_dir = 0;
|
||||
if (valid_trig)begin
|
||||
next_state = S_SEND_ECHO;
|
||||
end
|
||||
end
|
||||
|
||||
S_SEND_ECHO: begin
|
||||
sig_dir = 1; // Mettre en sortie
|
||||
|
||||
if (echo_sended) begin
|
||||
echo_sended = 0; // Reset flag
|
||||
next_state = S_WAIT_TRIG;
|
||||
end else begin
|
||||
next_state = S_SEND_ECHO;
|
||||
end
|
||||
end
|
||||
|
||||
default: begin
|
||||
sig_dir = 0;
|
||||
next_state = S_WAIT_TRIG;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state <= next_state;
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (state == S_MEASURE_TRIG) begin
|
||||
if (signal == 1) begin
|
||||
trig_counter <= trig_counter + 1;
|
||||
end else begin
|
||||
if (trig_counter >= TRIG_PULSE_CYCLES) begin
|
||||
valid_trig <= 1;
|
||||
end else begin
|
||||
valid_trig <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg [15:0] echo_delay_counter;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (state == S_SEND_ECHO) begin
|
||||
if (echo_delay_counter == 5800) begin //
|
||||
signal_out <= 0;
|
||||
echo_sended <= 1;
|
||||
end else begin
|
||||
signal_out <= 1;
|
||||
echo_delay_counter <= echo_delay_counter + 1;
|
||||
end
|
||||
end else begin
|
||||
echo_delay_counter <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,27 @@
|
||||
module distance_ws2812_display(
|
||||
input wire clk,
|
||||
input wire [8:0] distance, // distance mesurer
|
||||
output wire ws2812_dout // broche de données pour la LED WS2812
|
||||
);
|
||||
|
||||
reg [23:0] led_color; // couleur à envoyer à la LED (format RGB)
|
||||
|
||||
always @(posedge clk) begin
|
||||
// Mapper la distance sur une couleur
|
||||
if (distance < 100) begin
|
||||
led_color <= 24'hFF0000; // Rouge (proche)
|
||||
end else if (distance < 200) begin
|
||||
led_color <= 24'hFFFF00; // Jaune (distance moyenne)
|
||||
end else begin
|
||||
led_color <= 24'h00FF00; // Vert (très loin)
|
||||
end
|
||||
end
|
||||
|
||||
// Instance du module de transmission pour WS2812
|
||||
ws2812_driver ws2812_inst (
|
||||
.clk(clk),
|
||||
.color(led_color),
|
||||
.ws2812_dout(ws2812_dout)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,34 @@
|
||||
// Testbench pour distance_ws2812_display
|
||||
module tb_distance_ws2812_display;
|
||||
|
||||
reg clk;
|
||||
reg [8:0] distance;
|
||||
wire ws2812_dout;
|
||||
|
||||
// Instance du module à tester
|
||||
distance_ws2812_display uut (
|
||||
.clk(clk),
|
||||
.distance(distance),
|
||||
.ws2812_dout(ws2812_dout)
|
||||
);
|
||||
|
||||
always #5 clk = ~clk;
|
||||
integer i;
|
||||
initial begin
|
||||
// Initialiser les signaux
|
||||
clk = 0;
|
||||
distance = 0;
|
||||
|
||||
$dumpfile("distance_ws2812_display.vcd");
|
||||
$dumpvars(0, tb_distance_ws2812_display);
|
||||
|
||||
// Test de la conversion de distance en LED
|
||||
for (i = 0; i <= 380; i = i + 10) begin
|
||||
distance = i;
|
||||
#10;
|
||||
$display("Distance: %3d cm => dout: %b", distance, ws2812_dout);
|
||||
end
|
||||
|
||||
#100 $stop; // Arrêter la simulation après un certain temps
|
||||
end
|
||||
endmodule
|
||||
@@ -0,0 +1,27 @@
|
||||
module ws2812_driver(
|
||||
input wire clk,
|
||||
input wire [23:0] color, // couleur RGB (8 bits par composant)
|
||||
output reg ws2812_dout // broche de données vers la LED
|
||||
);
|
||||
reg [7:0] bit_count; // compteur de bits pour envoyer les données
|
||||
reg [23:0] shift_reg; // registre pour envoyer la couleur
|
||||
|
||||
always @(posedge clk) begin
|
||||
|
||||
if (bit_count == 0) begin
|
||||
shift_reg <= color; // Charger la couleur à transmettre
|
||||
ws2812_dout <= 1'b0; // Commencer par envoyer un "0"
|
||||
end else begin
|
||||
// Envoyer chaque bit un à un en contrôlant la durée de l'impulsion
|
||||
ws2812_dout <= shift_reg[23]; // Le bit le plus significatif
|
||||
shift_reg <= shift_reg << 1; // Décalage des bits
|
||||
end
|
||||
// Incrémentation du compteur de bits
|
||||
if (bit_count < 24)
|
||||
bit_count <= bit_count + 1;
|
||||
else
|
||||
bit_count <= 0; // Réinitialiser pour envoyer la prochaine couleur
|
||||
|
||||
end
|
||||
endmodule
|
||||
|
||||
420
Semaine_3/Capteur_recule_bidirectionel_V2/sim.out
Normal file
420
Semaine_3/Capteur_recule_bidirectionel_V2/sim.out
Normal file
@@ -0,0 +1,420 @@
|
||||
#!
|
||||
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 12;
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
|
||||
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2009.vpi";
|
||||
S_00000247b1636280 .scope package, "$unit" "$unit" 2 1;
|
||||
.timescale 0 0;
|
||||
S_00000247b1637ec0 .scope module, "tb_top_ultrasonic_led" "tb_top_ultrasonic_led" 3 3;
|
||||
.timescale -9 -12;
|
||||
o00000247b165a468 .functor BUFZ 1, c4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v00000247b16ac1d0_0 name=_ivl_0
|
||||
v00000247b16ac8b0_0 .var "clk", 0 0;
|
||||
v00000247b16ad5d0_0 .net "leds", 5 0, v00000247b162bdc0_0; 1 drivers
|
||||
RS_00000247b165a108 .resolv tri, L_00000247b16acdb0, L_00000247b16ac590;
|
||||
v00000247b16ac310_0 .net8 "sig", 0 0, RS_00000247b165a108; 2 drivers
|
||||
v00000247b16ad2b0_0 .var "sig_drive_enable", 0 0;
|
||||
v00000247b16ac3b0_0 .var "sig_driver", 0 0;
|
||||
v00000247b16ada30_0 .var "start", 0 0;
|
||||
E_00000247b1631690 .event anyedge, v00000247b162c5e0_0;
|
||||
L_00000247b16acdb0 .functor MUXZ 1, o00000247b165a468, v00000247b16ac3b0_0, v00000247b16ad2b0_0, C4<>;
|
||||
S_00000247b163de10 .scope module, "uut" "top_ultrasonic_led" 3 16, 4 1 0, S_00000247b1637ec0;
|
||||
.timescale -9 -12;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "start";
|
||||
.port_info 2 /INOUT 1 "sig";
|
||||
.port_info 3 /OUTPUT 6 "leds";
|
||||
v00000247b162c0e0_0 .net "clk", 0 0, v00000247b16ac8b0_0; 1 drivers
|
||||
v00000247b162c4a0_0 .net "distance", 15 0, v00000247b162c360_0; 1 drivers
|
||||
v00000247b162c860_0 .net "leds", 5 0, v00000247b162bdc0_0; alias, 1 drivers
|
||||
v00000247b162c900_0 .net8 "sig", 0 0, RS_00000247b165a108; alias, 2 drivers
|
||||
v00000247b16ad3f0_0 .net "start", 0 0, v00000247b16ada30_0; 1 drivers
|
||||
L_00000247b16add50 .part v00000247b162c360_0, 0, 9;
|
||||
S_00000247b163dfa0 .scope module, "led_display_inst" "distance_display_led" 4 19, 5 1 0, S_00000247b163de10;
|
||||
.timescale -9 -12;
|
||||
.port_info 0 /INPUT 9 "distance";
|
||||
.port_info 1 /OUTPUT 6 "leds";
|
||||
P_00000247b1636410 .param/l "LEVELS" 0 5 9, +C4<00000000000000000000000000000101>;
|
||||
P_00000247b1636448 .param/l "MAX_DIST" 0 5 8, +C4<00000000000000000000000101011101>;
|
||||
P_00000247b1636480 .param/l "MIN_DIST" 0 5 7, +C4<00000000000000000000000000000010>;
|
||||
P_00000247b16364b8 .param/l "PART_SIZE" 0 5 10, +C4<0000000000000000000000000001000101>;
|
||||
v00000247b162c2c0_0 .net "distance", 8 0, L_00000247b16add50; 1 drivers
|
||||
v00000247b162bdc0_0 .var "leds", 5 0;
|
||||
E_00000247b1631f10 .event anyedge, v00000247b162c2c0_0;
|
||||
S_00000247b163e130 .scope module, "ultrasonic_inst" "ultrasonic_fpga" 4 11, 6 1 0, S_00000247b163de10;
|
||||
.timescale -9 -12;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "start";
|
||||
.port_info 2 /INOUT 1 "sig";
|
||||
.port_info 3 /OUTPUT 16 "distance";
|
||||
.port_info 4 /OUTPUT 3 "state";
|
||||
P_00000247b164fb50 .param/l "CLK_FREQ" 0 6 2, +C4<00000001100110111111110011000000>;
|
||||
P_00000247b164fb88 .param/l "DIST_DIVISOR" 1 6 31, +C4<00000000000000000000011000011110>;
|
||||
P_00000247b164fbc0 .param/l "DONE" 1 6 27, C4<101>;
|
||||
P_00000247b164fbf8 .param/l "IDLE" 1 6 22, C4<000>;
|
||||
P_00000247b164fc30 .param/l "MAX_CM" 1 6 32, +C4<00000000000000000000000101011110>;
|
||||
P_00000247b164fc68 .param/l "MEASURE_ECHO" 1 6 26, C4<100>;
|
||||
P_00000247b164fca0 .param/l "TIMEOUT_CYCLES" 1 6 33, +C4<11111111111111111111100110001001>;
|
||||
P_00000247b164fcd8 .param/l "TRIG_HIGH" 1 6 23, C4<001>;
|
||||
P_00000247b164fd10 .param/l "TRIG_LOW" 1 6 24, C4<010>;
|
||||
P_00000247b164fd48 .param/l "TRIG_PULSE_CYCLES" 1 6 30, +C4<00000000000000000000000100001110>;
|
||||
P_00000247b164fd80 .param/l "WAIT_ECHO" 1 6 25, C4<011>;
|
||||
P_00000247b164fdb8 .param/l "WAIT_NEXT" 1 6 28, C4<110>;
|
||||
P_00000247b164fdf0 .param/l "WAIT_NEXT_CYCLES" 1 6 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>;
|
||||
o00000247b1659fe8 .functor BUFZ 1, c4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v00000247b162c540_0 name=_ivl_0
|
||||
v00000247b162bd20_0 .net "clk", 0 0, v00000247b16ac8b0_0; alias, 1 drivers
|
||||
v00000247b162c360_0 .var "distance", 15 0;
|
||||
v00000247b162c9a0_0 .var "distance_counter", 15 0;
|
||||
v00000247b162bf00_0 .var "echo_counter", 31 0;
|
||||
v00000247b162c680_0 .var "echo_div_counter", 31 0;
|
||||
v00000247b162c5e0_0 .net8 "sig", 0 0, RS_00000247b165a108; alias, 2 drivers
|
||||
v00000247b162c720_0 .var "sig_dir", 0 0;
|
||||
v00000247b162be60_0 .var "sig_int", 0 0;
|
||||
v00000247b162ca40_0 .var "sig_ok", 0 0;
|
||||
v00000247b162bbe0_0 .var "sig_out", 0 0;
|
||||
v00000247b162bfa0_0 .net "start", 0 0, v00000247b16ada30_0; alias, 1 drivers
|
||||
v00000247b162c400_0 .var "state", 2 0;
|
||||
v00000247b162c040_0 .var "trig_counter", 15 0;
|
||||
v00000247b162c7c0_0 .var "wait_counter", 31 0;
|
||||
E_00000247b1631f90 .event posedge, v00000247b162bd20_0;
|
||||
L_00000247b16ac590 .functor MUXZ 1, o00000247b1659fe8, v00000247b162bbe0_0, v00000247b162c720_0, C4<>;
|
||||
.scope S_00000247b163e130;
|
||||
T_0 ;
|
||||
%wait E_00000247b1631f90;
|
||||
%load/vec4 v00000247b162c5e0_0;
|
||||
%assign/vec4 v00000247b162be60_0, 0;
|
||||
%load/vec4 v00000247b162be60_0;
|
||||
%assign/vec4 v00000247b162ca40_0, 0;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_00000247b163e130;
|
||||
T_1 ;
|
||||
%wait E_00000247b1631f90;
|
||||
%load/vec4 v00000247b162c400_0;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.0, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.1, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.2, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.3, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.4, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.5, 6;
|
||||
%dup/vec4;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%cmp/u;
|
||||
%jmp/1 T_1.6, 6;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%jmp T_1.8;
|
||||
T_1.0 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000247b162bbe0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000247b162c720_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000247b162c360_0, 0;
|
||||
%load/vec4 v00000247b162bfa0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.9, 8;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000247b162c040_0, 0;
|
||||
T_1.9 ;
|
||||
%jmp T_1.8;
|
||||
T_1.1 ;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000247b162bbe0_0, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%assign/vec4 v00000247b162c720_0, 0;
|
||||
%load/vec4 v00000247b162c040_0;
|
||||
%pad/u 32;
|
||||
%cmpi/u 270, 0, 32;
|
||||
%jmp/0xz T_1.11, 5;
|
||||
%load/vec4 v00000247b162c040_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000247b162c040_0, 0;
|
||||
%jmp T_1.12;
|
||||
T_1.11 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000247b162c040_0, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
T_1.12 ;
|
||||
%jmp T_1.8;
|
||||
T_1.2 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000247b162bbe0_0, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000247b162c720_0, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%jmp T_1.8;
|
||||
T_1.3 ;
|
||||
%load/vec4 v00000247b162ca40_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.13, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000247b162bf00_0, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%jmp T_1.14;
|
||||
T_1.13 ;
|
||||
%load/vec4 v00000247b162bf00_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.15, 5;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000247b162c360_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%jmp T_1.16;
|
||||
T_1.15 ;
|
||||
%load/vec4 v00000247b162bf00_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000247b162bf00_0, 0;
|
||||
T_1.16 ;
|
||||
T_1.14 ;
|
||||
%jmp T_1.8;
|
||||
T_1.4 ;
|
||||
%load/vec4 v00000247b162ca40_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.17, 8;
|
||||
%load/vec4 v00000247b162bf00_0;
|
||||
%cmpi/u 4294965641, 0, 32;
|
||||
%jmp/0xz T_1.19, 5;
|
||||
%load/vec4 v00000247b162bf00_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000247b162bf00_0, 0;
|
||||
%jmp T_1.20;
|
||||
T_1.19 ;
|
||||
%pushi/vec4 0, 0, 16;
|
||||
%assign/vec4 v00000247b162c360_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
T_1.20 ;
|
||||
%jmp T_1.18;
|
||||
T_1.17 ;
|
||||
%load/vec4 v00000247b162bf00_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000247b162bf00_0, 0;
|
||||
%load/vec4 v00000247b162c680_0;
|
||||
%cmpi/u 1565, 0, 32;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.21, 5;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000247b162c680_0, 0;
|
||||
%load/vec4 v00000247b162c9a0_0;
|
||||
%addi 1, 0, 16;
|
||||
%assign/vec4 v00000247b162c9a0_0, 0;
|
||||
%jmp T_1.22;
|
||||
T_1.21 ;
|
||||
%load/vec4 v00000247b162c680_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000247b162c680_0, 0;
|
||||
T_1.22 ;
|
||||
%load/vec4 v00000247b162c9a0_0;
|
||||
%assign/vec4 v00000247b162c360_0, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
T_1.18 ;
|
||||
%jmp T_1.8;
|
||||
T_1.5 ;
|
||||
%load/vec4 v00000247b162bfa0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.23, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v00000247b162c7c0_0, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
%jmp T_1.24;
|
||||
T_1.23 ;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
T_1.24 ;
|
||||
%jmp T_1.8;
|
||||
T_1.6 ;
|
||||
%load/vec4 v00000247b162c7c0_0;
|
||||
%addi 1, 0, 32;
|
||||
%assign/vec4 v00000247b162c7c0_0, 0;
|
||||
%load/vec4 v00000247b162c7c0_0;
|
||||
%pad/u 64;
|
||||
%cmpi/u 2700000, 0, 64;
|
||||
%flag_inv 5; GE is !LT
|
||||
%jmp/0xz T_1.25, 5;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%assign/vec4 v00000247b162c400_0, 0;
|
||||
T_1.25 ;
|
||||
%jmp T_1.8;
|
||||
T_1.8 ;
|
||||
%pop/vec4 1;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_00000247b163dfa0;
|
||||
T_2 ;
|
||||
%wait E_00000247b1631f10;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 2, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.0, 5;
|
||||
%pushi/vec4 63, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.1;
|
||||
T_2.0 ;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 71, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.2, 5;
|
||||
%pushi/vec4 62, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.3;
|
||||
T_2.2 ;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 140, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.4, 5;
|
||||
%pushi/vec4 60, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.5;
|
||||
T_2.4 ;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 209, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.6, 5;
|
||||
%pushi/vec4 56, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.7;
|
||||
T_2.6 ;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 278, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.8, 5;
|
||||
%pushi/vec4 48, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.9;
|
||||
T_2.8 ;
|
||||
%load/vec4 v00000247b162c2c0_0;
|
||||
%pad/u 34;
|
||||
%cmpi/u 347, 0, 34;
|
||||
%flag_or 5, 4;
|
||||
%jmp/0xz T_2.10, 5;
|
||||
%pushi/vec4 32, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
%jmp T_2.11;
|
||||
T_2.10 ;
|
||||
%pushi/vec4 0, 0, 6;
|
||||
%store/vec4 v00000247b162bdc0_0, 0, 6;
|
||||
T_2.11 ;
|
||||
T_2.9 ;
|
||||
T_2.7 ;
|
||||
T_2.5 ;
|
||||
T_2.3 ;
|
||||
T_2.1 ;
|
||||
%jmp T_2;
|
||||
.thread T_2, $push;
|
||||
.scope S_00000247b1637ec0;
|
||||
T_3 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ac8b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ada30_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ac3b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ad2b0_0, 0, 1;
|
||||
%end;
|
||||
.thread T_3, $init;
|
||||
.scope S_00000247b1637ec0;
|
||||
T_4 ;
|
||||
%delay 18500, 0;
|
||||
%load/vec4 v00000247b16ac8b0_0;
|
||||
%inv;
|
||||
%store/vec4 v00000247b16ac8b0_0, 0, 1;
|
||||
%jmp T_4;
|
||||
.thread T_4;
|
||||
.scope S_00000247b1637ec0;
|
||||
T_5 ;
|
||||
%vpi_call/w 3 28 "$dumpfile", "top_ultrasonic_led.vcd" {0 0 0};
|
||||
%vpi_call/w 3 29 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000247b1637ec0 {0 0 0};
|
||||
%delay 100000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000247b16ada30_0, 0, 1;
|
||||
%delay 50000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ada30_0, 0, 1;
|
||||
T_5.0 ;
|
||||
%load/vec4 v00000247b16ac310_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 1, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 6;
|
||||
%cmpi/ne 1, 0, 1;
|
||||
%jmp/0xz T_5.1, 6;
|
||||
%wait E_00000247b1631690;
|
||||
%jmp T_5.0;
|
||||
T_5.1 ;
|
||||
%vpi_call/w 3 38 "$display", "TRIG HIGH at %t", $time {0 0 0};
|
||||
T_5.2 ;
|
||||
%load/vec4 v00000247b16ac310_0;
|
||||
%pad/u 32;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%cmp/e;
|
||||
%flag_get/vec4 6;
|
||||
%cmpi/ne 1, 0, 1;
|
||||
%jmp/0xz T_5.3, 6;
|
||||
%wait E_00000247b1631690;
|
||||
%jmp T_5.2;
|
||||
T_5.3 ;
|
||||
%vpi_call/w 3 41 "$display", "TRIG LOW at %t", $time {0 0 0};
|
||||
%delay 3000000, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000247b16ac3b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000247b16ad2b0_0, 0, 1;
|
||||
%delay 11600000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ac3b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000247b16ad2b0_0, 0, 1;
|
||||
%delay 200000000, 0;
|
||||
%vpi_call/w 3 56 "$display", "Distance mesur\303\251e : %d", v00000247b162c360_0 {0 0 0};
|
||||
%vpi_call/w 3 57 "$display", "LEDs affich\303\251es : %b", v00000247b16ad5d0_0 {0 0 0};
|
||||
%vpi_call/w 3 59 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_5;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 7;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"-";
|
||||
"tb_top_ultrasonic_led.v";
|
||||
"top_ultrasonic_led.v";
|
||||
"Distance_display_led/distance_display_led.v";
|
||||
"./Ultrasonic/ultrasonic_fpga.v";
|
||||
@@ -0,0 +1,62 @@
|
||||
`timescale 1ns/1ps
|
||||
|
||||
module tb_top_ultrasonic_led;
|
||||
|
||||
reg clk = 0;
|
||||
reg start = 0;
|
||||
wire sig;
|
||||
wire [5:0] leds;
|
||||
|
||||
// Simulation du comportement du capteur (via tri-state)
|
||||
reg sig_driver = 0;
|
||||
reg sig_drive_enable = 0;
|
||||
assign sig = sig_drive_enable ? sig_driver : 1'bz;
|
||||
|
||||
// Instance du module top
|
||||
top_ultrasonic_led uut (
|
||||
.clk(clk),
|
||||
.start(start),
|
||||
.sig(sig),
|
||||
.leds(leds)
|
||||
);
|
||||
|
||||
// Clock à 27 MHz ≈ 18.5 ns période
|
||||
always #18.5 clk = ~clk;
|
||||
|
||||
initial begin
|
||||
// Initialisation
|
||||
$dumpfile("top_ultrasonic_led.vcd");
|
||||
$dumpvars(0, tb_top_ultrasonic_led);
|
||||
|
||||
#100;
|
||||
start = 1;
|
||||
#50;
|
||||
start = 0;
|
||||
|
||||
// Attente du front montant TRIG
|
||||
wait (sig === 1);
|
||||
$display("TRIG HIGH at %t", $time);
|
||||
|
||||
wait (sig === 0);
|
||||
$display("TRIG LOW at %t", $time);
|
||||
|
||||
// Attente avant d'envoyer un echo simulé
|
||||
#3000;
|
||||
|
||||
// Simuler ECHO HIGH pendant un certain temps
|
||||
sig_driver = 1;
|
||||
sig_drive_enable = 1;
|
||||
#11600; // durée d'echo (ex : 10 cm -> ~580us => 580 * 27 clk = ~15660)
|
||||
sig_driver = 0;
|
||||
sig_drive_enable = 0;
|
||||
|
||||
// Attente que la mesure soit faite
|
||||
#200_000;
|
||||
|
||||
$display("Distance mesurée : %d", uut.ultrasonic_inst.distance);
|
||||
$display("LEDs affichées : %b", leds);
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -0,0 +1,24 @@
|
||||
module top_ultrasonic_led (
|
||||
input wire clk,
|
||||
input wire start, // bouton de déclenchement
|
||||
inout wire sig, // broche unique pour trigger + echo
|
||||
output wire [5:0] leds // LEDs pour affichage distance
|
||||
);
|
||||
|
||||
wire [15:0] distance;
|
||||
|
||||
// Module de mesure (version bidirectionnelle du capteur)
|
||||
ultrasonic_fpga ultrasonic_inst (
|
||||
.clk(clk),
|
||||
.start(start),
|
||||
.sig(sig),
|
||||
.distance(distance)
|
||||
);
|
||||
|
||||
// Module d'affichage LEDs
|
||||
distance_display_led led_display_inst (
|
||||
.distance(distance),
|
||||
.leds(leds)
|
||||
);
|
||||
|
||||
endmodule
|
||||
24762
Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.vcd
Normal file
24762
Semaine_3/Capteur_recule_bidirectionel_V2/top_ultrasonic_led.vcd
Normal file
File diff suppressed because it is too large
Load Diff
85
Semaine_3/Projet_esp32/Projet_esp32.md
Normal file
85
Semaine_3/Projet_esp32/Projet_esp32.md
Normal file
@@ -0,0 +1,85 @@
|
||||
# Projet FPGA (Tang Nano 20K) + ESP32
|
||||
|
||||
## Objectif global
|
||||
|
||||
Le but est de pouvoir se connecter à l’ESP32 via Wi-Fi, et de communiquer avec un PC (ou autre appareil USB connecté au FPGA).
|
||||
L’ESP32 agit comme **esclave** pour le FPGA et sert uniquement de **portail Wi-Fi**.
|
||||
Le FPGA fait le lien entre les appareils Wi-Fi et le périphérique USB.
|
||||
|
||||
|
||||
---
|
||||
|
||||
## Rôles des composants
|
||||
|
||||
### FPGA (Tang Nano 20K)
|
||||
- Gère l’interface UART avec l’ESP32
|
||||
- Gère la communication USB avec le PC
|
||||
- Fait le routage bidirectionnel des données (mux / buffer intelligent)
|
||||
|
||||
### ESP32
|
||||
- Crée un réseau Wi-Fi local
|
||||
- Écoute via une connexion UART avec le FPGA
|
||||
- Reçoit les commandes du FPGA et envoie les données des clients Wi-Fi
|
||||
|
||||
### PC (ou autre appareil USB)
|
||||
- Envoie et reçoit des données (via terminal série ou logiciel personnalisé)
|
||||
|
||||
---
|
||||
|
||||
## Architecture
|
||||
|
||||
```
|
||||
[ PC via USB ]
|
||||
│
|
||||
┌───────▼────────┐
|
||||
│ uart_usb │ <— UART avec le PC
|
||||
└──────┬─────────┘
|
||||
│
|
||||
▼
|
||||
┌──────────────┐
|
||||
│ uart_core │ <— Routeur/contrôleur central
|
||||
└────┬────┬────┘
|
||||
│ │
|
||||
┌─────────────┘ └────────────┐
|
||||
▼ ▼
|
||||
[uart_wifi] [user_logic] (LEDs)
|
||||
<— UART avec ESP32 (comporte les modules fonctionnels)
|
||||
```
|
||||
|
||||
---
|
||||
|
||||
## Détails des modules
|
||||
|
||||
### `uart_usb`
|
||||
- Interface UART vers le PC (via USB-UART)
|
||||
- Peut utiliser un convertisseur USB-UART via `uart_rx_pc` / `uart_tx_pc`
|
||||
- Fournit :
|
||||
- `rx_data`, `rx_valid`, `rx_ready`
|
||||
- `tx_data`, `tx_valid`, `tx_ready`
|
||||
|
||||
### `uart_wifi`
|
||||
- Interface UART avec l’ESP32
|
||||
- Même interface que `uart_usb`, mais avec `uart_rx_esp` / `uart_tx_esp`
|
||||
- Sert à la communication Wi-Fi
|
||||
|
||||
### `uart_core`
|
||||
- Module central de routage UART
|
||||
- Gère la logique de communication :
|
||||
- Lecture des commandes depuis le PC → envoie à l’ESP32
|
||||
- Réception de réponse de l’ESP32 → envoie au PC
|
||||
- Peut être codé comme une FSM maître ou un router simple
|
||||
|
||||
---
|
||||
|
||||
## Signaux principaux
|
||||
|
||||
| Signal | Description |
|
||||
|------------------------|------------------------------------------------------|
|
||||
| `uart_rx_pc` | UART RX depuis le PC |
|
||||
| `uart_tx_pc` | UART TX vers le PC |
|
||||
| `uart_rx_esp` | UART RX depuis l’ESP32 |
|
||||
| `uart_tx_esp` | UART TX vers l’ESP32 |
|
||||
| `fifo_rx_pc_to_esp` | Données du PC à transférer à l’ESP32 |
|
||||
| `fifo_rx_esp_to_pc` | Données de l’ESP32 à transférer au PC |
|
||||
| `link_manager` | Logique de contrôle des transferts entre buffers/UART|
|
||||
| `status_led` | Gestion des LEDs de statut |
|
||||
233
Semaine_3/Projet_esp32/esp32_code/Projet_code/ESP32/ESP32.ino
Normal file
233
Semaine_3/Projet_esp32/esp32_code/Projet_code/ESP32/ESP32.ino
Normal file
@@ -0,0 +1,233 @@
|
||||
#include <WiFi.h>
|
||||
#include <WebServer.h>
|
||||
#include "esp_wifi.h"
|
||||
|
||||
const char* ssid = "ESP32-Louis";
|
||||
const char* password = "motdepasse";
|
||||
|
||||
WebServer server(80);
|
||||
|
||||
void handleRoot() {
|
||||
digitalWrite(2,HIGH);
|
||||
wifi_sta_list_t sta_list;
|
||||
esp_wifi_ap_get_sta_list(&sta_list);
|
||||
|
||||
String page = "";
|
||||
page += "<!DOCTYPE html>";
|
||||
page += "<html>";
|
||||
page += "<head>";
|
||||
page += "<title>ESP32</title>";
|
||||
page += "<meta charset=\"UTF-8\">";
|
||||
page += "</head>";
|
||||
page += "<body>";
|
||||
page += "<h1>Appareils connectés à l'ESP32</h1>";
|
||||
page += "<ul>";
|
||||
|
||||
page += "<ul>";
|
||||
|
||||
for (int i = 0; i < sta_list.num; i++) {
|
||||
const wifi_sta_info_t& client = sta_list.sta[i];
|
||||
char macStr[18];
|
||||
snprintf(macStr, sizeof(macStr),
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
client.mac[0], client.mac[1], client.mac[2],
|
||||
client.mac[3], client.mac[4], client.mac[5]);
|
||||
page += "<li>MAC : ";
|
||||
page += macStr;
|
||||
page += "</li>";
|
||||
}
|
||||
|
||||
page += "</ul>";
|
||||
page += "<p>Nombre total : " + String(sta_list.num) + "</p>";
|
||||
|
||||
page += "</body></html>";
|
||||
|
||||
server.send(200, "text/html", page);
|
||||
digitalWrite(2,LOW);
|
||||
}
|
||||
|
||||
void onClientConnected(WiFiEvent_t event, WiFiEventInfo_t info) {
|
||||
digitalWrite(2, HIGH);
|
||||
|
||||
const wifi_event_ap_staconnected_t* conn = reinterpret_cast<const wifi_event_ap_staconnected_t*>(&info);
|
||||
|
||||
|
||||
byte packet[11]; // 2 header + 1 code + 6 MAC + 1 fin
|
||||
packet[0] = 0x02;
|
||||
packet[1] = 0x02;
|
||||
packet[2] = 0x01;
|
||||
|
||||
// Copier l'adr MAC dans le tableau
|
||||
memcpy(&packet[3], conn->mac, 6);
|
||||
|
||||
packet[9] = 0x1B; // marqueur avant fin
|
||||
packet[10] = 0x03; // fin de trame
|
||||
|
||||
Serial.write(packet, sizeof(packet));
|
||||
digitalWrite(2, LOW);
|
||||
}
|
||||
|
||||
void onClientDisconnected(WiFiEvent_t event, WiFiEventInfo_t info) {
|
||||
digitalWrite(2, HIGH);
|
||||
|
||||
const wifi_event_ap_stadisconnected_t* disc = reinterpret_cast<const wifi_event_ap_stadisconnected_t*>(&info);
|
||||
|
||||
byte packet[12];
|
||||
packet[0] = 0x02;
|
||||
packet[1] = 0x02; // OP_CODE: Connection Update
|
||||
packet[2] = 0x00; // Disconnected
|
||||
|
||||
memcpy(&packet[3], disc->mac, 6); // MAC address
|
||||
|
||||
packet[9] = 0x1B; // marqueur avant fin
|
||||
packet[10] = 0x03; // fin de trame
|
||||
packet[11] = '\n'; // (optionnel, pour debug dans terminal série)
|
||||
|
||||
Serial.write(packet, 11); // <= envoie bien 11 octets, pas 12 (on ne compte pas le \n ici si tu veux l’ignorer)
|
||||
digitalWrite(2, LOW);
|
||||
}
|
||||
|
||||
#define BUFFER_SIZE 64
|
||||
uint8_t rxBuffer[BUFFER_SIZE];
|
||||
uint8_t rxIndex = 0;
|
||||
bool inFrame = false;
|
||||
|
||||
void processCommand(uint8_t* data, int length) {
|
||||
// Vérifie la validité de la trame
|
||||
if (length < 4 || data[0] != 0x02 || data[length - 2] != 0x1B || data[length - 1] != 0x03) {
|
||||
byte packet[] = {0x02, 0x00, 0x03, 0x1B, 0x03}; // Erreur : Trame invalide
|
||||
Serial.write(packet, sizeof(packet));
|
||||
return;
|
||||
}
|
||||
|
||||
uint8_t type = data[1];
|
||||
|
||||
switch (type) {
|
||||
|
||||
case 0x01: { // Wi-Fi State
|
||||
bool wifiUp = WiFi.status() == WL_CONNECTED;
|
||||
byte packet[] = {0x02, 0x01, wifiUp ? 0x01 : 0x00, 0x1B, 0x03};
|
||||
Serial.write(packet, sizeof(packet));
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x03: { // Request Connected Devices
|
||||
wifi_sta_list_t staList;
|
||||
if (esp_wifi_ap_get_sta_list(&staList) == ESP_OK) {
|
||||
byte packet[3 + 1 + 6 * 10 + 2]; // max 10 clients
|
||||
uint8_t index = 0;
|
||||
packet[index++] = 0x02;
|
||||
packet[index++] = 0x04;
|
||||
packet[index++] = staList.num; // LEN
|
||||
|
||||
for (int i = 0; i < staList.num; i++) {
|
||||
memcpy(&packet[index], staList.sta[i].mac, 6);
|
||||
index += 6;
|
||||
}
|
||||
|
||||
packet[index++] = 0x1B;
|
||||
packet[index++] = 0x03;
|
||||
|
||||
Serial.write(packet, index);
|
||||
} else {
|
||||
byte error[] = {0x02, 0x00, 0x02, 0x1B, 0x03}; // Erreur : args
|
||||
Serial.write(error, sizeof(error));
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 0x05: { // Send Message
|
||||
if (length < 12) {
|
||||
byte packet[] = {0x02, 0x00, 0x02, 0x1B, 0x03}; // args error
|
||||
Serial.write(packet, sizeof(packet));
|
||||
break;
|
||||
}
|
||||
|
||||
uint8_t* mac = &data[2];
|
||||
uint8_t msgLen = data[8];
|
||||
|
||||
if (length != 9 + msgLen + 2) {
|
||||
byte packet[] = {0x02, 0x00, 0x04, 0x1B, 0x03}; // too long trame
|
||||
Serial.write(packet, sizeof(packet));
|
||||
break;
|
||||
}
|
||||
|
||||
// Ici tu pourrais ajouter une logique pour router le message au bon appareil (plus tard)
|
||||
// ACK possible :
|
||||
byte ack[] = {0x02, 0x04, 0x01, 0x1B, 0x03}; // ACK
|
||||
Serial.write(ack, sizeof(ack));
|
||||
break;
|
||||
}
|
||||
|
||||
default: {
|
||||
byte packet[] = {0x02, 0x00, 0x01, 0x1B, 0x03}; // Erreur : commande inconnue
|
||||
Serial.write(packet, sizeof(packet));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void setup() {
|
||||
Serial.begin(115200);
|
||||
if (!WiFi.softAP(ssid, password)) {
|
||||
byte packet[] = {0x02, 0x01, 0x00, 0x03};
|
||||
Serial.write(packet, sizeof(packet));
|
||||
}
|
||||
|
||||
WiFi.onEvent(onClientConnected, ARDUINO_EVENT_WIFI_AP_STACONNECTED);
|
||||
WiFi.onEvent(onClientDisconnected, ARDUINO_EVENT_WIFI_AP_STADISCONNECTED);
|
||||
|
||||
delay(1000); // Donne un peu de temps pour démarrer le WiFi
|
||||
|
||||
server.on("/", handleRoot);
|
||||
server.begin();
|
||||
|
||||
pinMode(2, OUTPUT);
|
||||
|
||||
byte packet[] = {0x02, 0x01, 0x01, 0x03};
|
||||
Serial.write(packet, sizeof(packet));
|
||||
|
||||
}
|
||||
|
||||
void loop() {
|
||||
server.handleClient();
|
||||
|
||||
bool escaping = false;
|
||||
|
||||
while (Serial.available()) {
|
||||
uint8_t b = Serial.read();
|
||||
|
||||
if (!inFrame) {
|
||||
if (b == 0x02) {
|
||||
inFrame = true;
|
||||
rxIndex = 0;
|
||||
rxBuffer[rxIndex++] = b;
|
||||
}
|
||||
continue;
|
||||
}
|
||||
|
||||
if (escaping) {
|
||||
if (rxIndex < BUFFER_SIZE) {
|
||||
rxBuffer[rxIndex++] = b;
|
||||
}
|
||||
escaping = false;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (b == 0x1B) {
|
||||
escaping = true;
|
||||
} else if (b == 0x03) {
|
||||
rxBuffer[rxIndex++] = b;
|
||||
processCommand(rxBuffer, rxIndex);
|
||||
inFrame = false;
|
||||
rxIndex = 0;
|
||||
} else {
|
||||
if (rxIndex < BUFFER_SIZE) {
|
||||
rxBuffer[rxIndex++] = b;
|
||||
} else {
|
||||
inFrame = false;
|
||||
rxIndex = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
28
Semaine_3/Projet_esp32/esp32_code/Projet_code/esp32_read.py
Normal file
28
Semaine_3/Projet_esp32/esp32_code/Projet_code/esp32_read.py
Normal file
@@ -0,0 +1,28 @@
|
||||
import serial
|
||||
|
||||
def main():
|
||||
try:
|
||||
with serial.Serial('COM5', 115200, timeout=1) as ser:
|
||||
buffer = []
|
||||
while True:
|
||||
byte = ser.read(1)
|
||||
if byte:
|
||||
value = byte[0]
|
||||
buffer.append(value)
|
||||
print(f"Reçu: {value:#04x}")
|
||||
|
||||
# Vérifie début de trame
|
||||
if len(buffer) == 1 and buffer[0] != 0x02:
|
||||
buffer.clear()
|
||||
|
||||
# Vérifie fin de trame
|
||||
if len(buffer) >= 3 and buffer[-2] == 0x1B and buffer[-1] == 0x03:
|
||||
print("\n=== Trame complète reçue ===")
|
||||
print("Trame :", ' '.join(f"{b:#04x}" for b in buffer))
|
||||
print("=============================\n")
|
||||
buffer.clear()
|
||||
except serial.SerialException as e:
|
||||
print("Erreur de port série :", e)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@@ -0,0 +1,54 @@
|
||||
import serial
|
||||
|
||||
def read_frame(ser):
|
||||
frame = []
|
||||
in_frame = False
|
||||
|
||||
while True:
|
||||
byte = ser.read()
|
||||
if not byte:
|
||||
continue
|
||||
b = byte[0]
|
||||
if not in_frame:
|
||||
if b == 0x02:
|
||||
frame = [b]
|
||||
in_frame = True
|
||||
else:
|
||||
frame.append(b)
|
||||
if len(frame) >= 2 and frame[-2] == 0x1B and frame[-1] == 0x03:
|
||||
return frame
|
||||
|
||||
def interpret_frame(frame):
|
||||
if len(frame) < 4 or frame[0] != 0x02 or frame[-2:] != [0x1B, 0x03]:
|
||||
return "Trame invalide"
|
||||
|
||||
op_code = frame[1]
|
||||
if op_code == 0x00:
|
||||
return f"[Erreur] Code: {hex(frame[2])}"
|
||||
elif op_code == 0x01:
|
||||
state = frame[2]
|
||||
return f"[Wi-Fi] {'UP' if state == 1 else 'DOWN'}"
|
||||
elif op_code == 0x02:
|
||||
status = 'Connecté' if frame[2] == 0x01 else 'Déconnecté'
|
||||
mac = ':'.join(f"{b:02X}" for b in frame[3:9])
|
||||
return f"[Connexion] {status} - {mac}"
|
||||
elif op_code == 0x03:
|
||||
return "[Demande appareils connectés]"
|
||||
elif op_code == 0x04:
|
||||
mac = ':'.join(f"{b:02X}" for b in frame[2:8])
|
||||
length = frame[8]
|
||||
msg = bytes(frame[9:9+length]).decode(errors='ignore')
|
||||
return f"[Message] à {mac} : {msg}"
|
||||
else:
|
||||
return f"[OpCode inconnu] {hex(op_code)}"
|
||||
|
||||
def main():
|
||||
with serial.Serial('COM5', 115200, timeout=1) as ser:
|
||||
print("Lecture des trames...")
|
||||
while True:
|
||||
frame = read_frame(ser)
|
||||
info = interpret_frame(frame)
|
||||
print(info)
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
@@ -0,0 +1,60 @@
|
||||
import serial
|
||||
import time
|
||||
|
||||
START_BYTE = 0x02
|
||||
END_BYTES = [0x1B, 0x03]
|
||||
|
||||
def build_command(opcode, payload=b''):
|
||||
frame = bytearray()
|
||||
frame.append(START_BYTE)
|
||||
frame.append(opcode)
|
||||
frame.extend(payload)
|
||||
frame.extend(END_BYTES)
|
||||
return frame
|
||||
|
||||
def send_command(ser, opcode, payload=b''):
|
||||
frame = build_command(opcode, payload)
|
||||
print(f"Envoi : {[hex(b) for b in frame]}")
|
||||
ser.write(frame)
|
||||
|
||||
def main():
|
||||
port = 'COM5'
|
||||
baud = 115200
|
||||
|
||||
try:
|
||||
with serial.Serial(port, baud, timeout=2) as ser:
|
||||
while True:
|
||||
print("\nCommandes disponibles :")
|
||||
print("1. État du Wi-Fi")
|
||||
print("2. Liste des clients connectés")
|
||||
print("3. Envoyer un message")
|
||||
print("4. Quitter")
|
||||
|
||||
choix = input("Choix (1-4) : ")
|
||||
|
||||
if choix == "1":
|
||||
send_command(ser, 0x01)
|
||||
elif choix == "2":
|
||||
send_command(ser, 0x03)
|
||||
elif choix == "3":
|
||||
msg = input("Message à envoyer : ")
|
||||
msg_bytes = msg.encode('utf-8')
|
||||
send_command(ser, 0x05, msg_bytes)
|
||||
elif choix == "4":
|
||||
print("Fermeture.")
|
||||
break
|
||||
else:
|
||||
print("Choix invalide.")
|
||||
|
||||
time.sleep(0.5)
|
||||
|
||||
print("Réponse reçue :")
|
||||
while ser.in_waiting:
|
||||
byte = ser.read(1)
|
||||
print(f"Reçu : 0x{byte[0]:02X}")
|
||||
|
||||
except serial.SerialException as e:
|
||||
print(f"Erreur de port série : {e}")
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
106
Semaine_3/Projet_esp32/esp32_code/Wifi_ap/Wifi_ap.ino
Normal file
106
Semaine_3/Projet_esp32/esp32_code/Wifi_ap/Wifi_ap.ino
Normal file
@@ -0,0 +1,106 @@
|
||||
#include <WiFi.h>
|
||||
#include <WebServer.h>
|
||||
#include "esp_wifi.h"
|
||||
|
||||
const char* ssid = "ESP32-Louis";
|
||||
const char* password = "motdepasse";
|
||||
|
||||
WebServer server(80);
|
||||
|
||||
void handleRoot() {
|
||||
digitalWrite(2,HIGH);
|
||||
wifi_sta_list_t sta_list;
|
||||
esp_wifi_ap_get_sta_list(&sta_list);
|
||||
|
||||
String page = "";
|
||||
page += "<!DOCTYPE html>";
|
||||
page += "<html>";
|
||||
page += "<head>";
|
||||
page += "<title>ESP32</title>";
|
||||
page += "<meta charset=\"UTF-8\">";
|
||||
page += "</head>";
|
||||
page += "<body>";
|
||||
page += "<h1>Appareils connectés à l'ESP32</h1>";
|
||||
page += "<ul>";
|
||||
|
||||
page += "<ul>";
|
||||
|
||||
for (int i = 0; i < sta_list.num; i++) {
|
||||
const wifi_sta_info_t& client = sta_list.sta[i];
|
||||
char macStr[18];
|
||||
snprintf(macStr, sizeof(macStr),
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
client.mac[0], client.mac[1], client.mac[2],
|
||||
client.mac[3], client.mac[4], client.mac[5]);
|
||||
page += "<li>MAC : ";
|
||||
page += macStr;
|
||||
page += "</li>";
|
||||
}
|
||||
|
||||
page += "</ul>";
|
||||
page += "<p>Nombre total : " + String(sta_list.num) + "</p>";
|
||||
|
||||
page += "</body></html>";
|
||||
|
||||
server.send(200, "text/html", page);
|
||||
digitalWrite(2,LOW);
|
||||
}
|
||||
|
||||
void onClientConnected(WiFiEvent_t event, WiFiEventInfo_t info) {
|
||||
digitalWrite(2,HIGH);
|
||||
|
||||
wifi_sta_list_t sta_list;
|
||||
esp_wifi_ap_get_sta_list(&sta_list);
|
||||
|
||||
for (int i = 0; i < sta_list.num; i++) {
|
||||
const wifi_sta_info_t& client = sta_list.sta[i];
|
||||
char macStr[18];
|
||||
snprintf(macStr, sizeof(macStr),
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
client.mac[0], client.mac[1], client.mac[2],
|
||||
client.mac[3], client.mac[4], client.mac[5]);
|
||||
Serial.print("Adresse MAC : ");
|
||||
Serial.println(macStr);
|
||||
}
|
||||
|
||||
digitalWrite(2,LOW);
|
||||
}
|
||||
|
||||
void onClientDisconnected(WiFiEvent_t event, WiFiEventInfo_t info) {
|
||||
digitalWrite(2,HIGH);
|
||||
|
||||
wifi_sta_list_t sta_list;
|
||||
esp_wifi_ap_get_sta_list(&sta_list);
|
||||
|
||||
for (int i = 0; i < sta_list.num; i++) {
|
||||
const wifi_sta_info_t& client = sta_list.sta[i];
|
||||
char macStr[18];
|
||||
snprintf(macStr, sizeof(macStr),
|
||||
"%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
client.mac[0], client.mac[1], client.mac[2],
|
||||
client.mac[3], client.mac[4], client.mac[5]);
|
||||
Serial.print("",macStr);
|
||||
}
|
||||
|
||||
digitalWrite(2,LOW);
|
||||
}
|
||||
|
||||
void setup() {
|
||||
Serial.begin(115200);
|
||||
WiFi.softAP(ssid, password);
|
||||
|
||||
WiFi.onEvent(onClientConnected, ARDUINO_EVENT_WIFI_AP_STACONNECTED);
|
||||
WiFi.onEvent(onClientDisconnected, ARDUINO_EVENT_WIFI_AP_STADISCONNECTED);
|
||||
|
||||
delay(1000); // Donne un peu de temps pour démarrer le WiFi
|
||||
|
||||
|
||||
server.on("/", handleRoot);
|
||||
server.begin();
|
||||
|
||||
pinMode(2, OUTPUT);
|
||||
}
|
||||
|
||||
void loop() {
|
||||
server.handleClient();
|
||||
}
|
||||
@@ -0,0 +1,11 @@
|
||||
void setup() {
|
||||
Serial.begin(115200);
|
||||
pinMode(2, OUTPUT); // LED intégrée sur beaucoup d'ESP32
|
||||
}
|
||||
|
||||
void loop() {
|
||||
digitalWrite(2, HIGH);
|
||||
delay(500);
|
||||
digitalWrite(2, LOW);
|
||||
delay(500);
|
||||
}
|
||||
81
Semaine_3/Projet_esp32/protocole_esp_fpga.md
Normal file
81
Semaine_3/Projet_esp32/protocole_esp_fpga.md
Normal file
@@ -0,0 +1,81 @@
|
||||
# Protocole between FPGA and ESP32
|
||||
|
||||
Ce protocole permet la communication entre le FPGA et l'ESP32 via UART, principalement pour transférer des données ou des commandes de contrôle simples.
|
||||
|
||||
---
|
||||
|
||||
## Structure générale des trames
|
||||
|
||||
Chaque trame est encadrée par des caractères spéciaux :
|
||||
|
||||
- **ESCAPE** (Before special char) : `0x1B`
|
||||
- **STX** (Start of Text) : `0x02`
|
||||
- **ETX** (End of Text) : `0x03`
|
||||
|
||||
|
||||
**Format de trame :**
|
||||
```
|
||||
0x02 OP_CODE VALUE_1 VALUE_2 ... 0x1B 0x03
|
||||
```
|
||||
---
|
||||
|
||||
## Détail des commandes
|
||||
|
||||
| OP_CODE | Nom | Description | Format |
|
||||
|---------|---------------------------|---------------------------------------------------------|-------------------------------------------------------------------------------|
|
||||
| 0x00 | Error | Indique une erreur | `0x02 0x00 [ERROR_CODE] 0x1B 0x03` |
|
||||
| 0x01 | Wi-Fi State | Indique l'état du Wi-Fi (0 = down, 1 = up) | `0x02 0x01 [0x00/0x01] 0x1B 0x03` |
|
||||
| 0x02 | Connection Update | Notification de connexion ou déconnexion d’un appareil | `0x02 0x02 [0x00/0x01] [MAC_ADDR (6 bytes)] 0x1B 0x03` |
|
||||
| 0x03 | Request Connected Devices | Demande la liste des appareils connectés | `0x02 0x03 0x1B 0x03` |
|
||||
| 0x04 | Send Connected Devices | Envoie la liste des appareil connecter | `0x02 0x04 [LEN (1 byte)] [MAC_LIST (n bytes)[MAC_ADDR (6 bytes)]] 0x1B 0x03` |
|
||||
| 0x05 | Send Message | Envoie un message à un appareil connecté via son MAC | `0x02 0x05 [MAC_ADDR (6 bytes)] [LEN (1 byte)] [MESSAGE] 0x1B 0x03` |
|
||||
|
||||
---
|
||||
|
||||
## Détail des code erreur
|
||||
|
||||
| ERROR_CODE | Description |
|
||||
|---------------|---------------------------------------------------------------|
|
||||
| 0x00 | |
|
||||
| 0x01 | Unknow command |
|
||||
| 0x02 | Args error |
|
||||
| 0x03 | Invalid Trame |
|
||||
| 0x04 | Too long trame |
|
||||
|
||||
---
|
||||
|
||||
## Détails des champs
|
||||
|
||||
- **MAC_ADDR** : 6 octets représentant l’adresse MAC du destinataire.
|
||||
- **LEN** : Longueur du message à envoyer (1 octet).
|
||||
- **MESSAGE** : Suite d’octets de taille `LEN` représentant le message (binaire ou texte selon le contexte).
|
||||
|
||||
---
|
||||
|
||||
## Exemples
|
||||
|
||||
### Exemple 1 : Wi-Fi actif
|
||||
```
|
||||
0x02 0x01 0x01 0x03
|
||||
```
|
||||
→ Indique que le Wi-Fi est actif.
|
||||
|
||||
### Exemple 2 : Connexion d'un appareil
|
||||
```
|
||||
0x02 0x02 0x01 0x12 0x34 0x56 0x78 0x9A 0xBC 0x03
|
||||
```
|
||||
→ Un appareil avec l’adresse MAC `12:34:56:78:9A:BC` vient de se connecter.
|
||||
|
||||
### Exemple 3 : Envoi de message
|
||||
```
|
||||
0x02 0x04 0x12 0x34 0x56 0x78 0x9A 0xBC 0x05 0x48 0x65 0x6C 0x6C 0x6F 0x03
|
||||
```
|
||||
→ Envoi du message `"Hello"` à l’appareil `12:34:56:78:9A:BC`.
|
||||
|
||||
---
|
||||
|
||||
## Remarques
|
||||
|
||||
- Aucune vérification CRC/Checksum n’est ajoutée pour le moment (possible amélioration future).
|
||||
- Le protocole est extensible : il suffit d’ajouter de nouveaux OP_CODEs au besoin.
|
||||
|
||||
16
Semaine_3/README.md
Normal file
16
Semaine_3/README.md
Normal file
@@ -0,0 +1,16 @@
|
||||
## Semaine 2
|
||||
|
||||
### Jour 6
|
||||
|
||||
**Matin :**
|
||||
- Remise en contexte
|
||||
- Réflexion sur un projet combinant FPGA (Tang Nano 20K) + ESP32 :
|
||||
- Objectif : se connecter à l’ESP32 (Wi-Fi) → communiquer avec le PC (via USB au FPGA)
|
||||
- L’ESP32 agit comme un esclave, servant uniquement de portail Wi-Fi
|
||||
- Le FPGA fait le lien entre Wi-Fi et périphériques USB
|
||||
|
||||
**Architecture prévue :**
|
||||
[ PC via USB-C ] ←→ [ FPGA (Tang Nano 20K) ] ←→ [ ESP32 ] ←→ [ Clients en Wi-Fi ]
|
||||
|
||||
**Après-midi :**
|
||||
- Documentation sur l’esp 32
|
||||
Reference in New Issue
Block a user