Init du DHT11 Interface

Semaine_5/DHT11/src/verilog/dht11_interface.v

@@ -0,0 +1,35 @@
+module dht11_interface (
+    input wire          i_clk, // 27 MHz
+    inout wire          io_dht11_sig,
+    output wire         o_dht11_data_ready,
+    output wire [7:0]   o_temp_data,
+    output wire [7:0]   o_hum_data,
+    output wire         o_dht11_error
+);
+
+    // === DHT11 INTERFACE ===
+    // Le module DHT11 est connecté à la broche io_dht11_sig.
+    // La communication se fait en mode bidirectionnel.
+
+    wire sig_dir;
+    wire sig_out;
+    
+    assign io_dht11_sig = sig_dir ? sig_out : 1'bz;
+
+
+    // === FSM ===
+    localparam  IDLE            = 3'd0, // Pull up la ligne
+
+                START           = 3'd1, // Pull low 18ms
+                WAIT_RESPONSE   = 3'd2, // Release la ligne (entre 20 et 40us)
+
+                READ_HUM_INT    = 3'd3, 
+                READ_HUM_DEC    = 3'd4;
+                READ_TEMP_INT   = 3'd5, 
+                READ_TEMP_DEC   = 3'd6,
+                READ_CHECKSUM   = 3'd7, // Last 8 bits of {1st Byte + 2nd Byte + 3rd Byte+ 4th Byte}
+
+                DONE            = 3'd8;
+               
+
+endmodule