Init du DHT11 Interface

Semaine_5/DHT11/tests/verilog/tb_dht11.v

@@ -0,0 +1,27 @@
+`timescale 1ns/1ps
+
+module tb_dht11;
+
+    reg clk = 0;
+    always #18.5 clk = ~clk; // Génère une clock 27 MHz
+
+    // === Simulation du module DHT11 ===
+
+
+    // === Module DHT11 INTERFACE ===
+
+
+    // === TEST SEQUENCE ===
+    initial begin
+        $dumpfile("runs/wave.vcd");
+        $dumpvars(0, tb_dht11);
+
+        $display("==== Start DHT11 Test ====");
+        
+        
+
+        $display("==== End DHT11 Test ====");
+        $finish;
+    end
+
+endmodule