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FPGA_ESP32_WIFI_Fonctionnel 3MB

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This commit is contained in:
Louis TANCHOU
2025-06-03 09:04:26 +02:00
parent 3541476e9a
commit 20cbaace08
8 changed files with 49 additions and 38 deletions
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2
Semaine_7/ESP32/leds_commands/IP/verilog/rxuartlite.v
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@@ -52,7 +52,7 @@ module rxuartlite #(
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 27MHz
`endif
localparam TB = TIMER_BITS,
//

9
Semaine_7/ESP32/leds_commands/IP/verilog/uart_rx_fifo.v
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@@ -19,8 +19,15 @@ module uart_rx_fifo #(
wire fifo_empty;
wire fifo_full;
localparam integer CPB = CLK_FREQ/BAUD_RATE;
// UART Receiver instance
rxuartlite uart_rx_inst (
rxuartlite
#(
.CLOCKS_PER_BAUD(CPB),
.TIMER_BITS($clog2(CPB)+1)
) uart_rx_inst
(
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),

7
Semaine_7/ESP32/leds_commands/IP/verilog/uart_tx_fifo.v
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@@ -45,7 +45,12 @@ module uart_tx_fifo #(
);
// UART TX instantiation
txuartlite uart_tx_inst (
txuartlite
#(
.CLOCKS_PER_BAUD(CLK_FREQ/BAUD_RATE),
.TIMING_BITS($clog2(CLK_FREQ/BAUD_RATE)+1)
) uart_tx_inst
(
.i_clk(clk),
.i_reset(1'b0),
.i_wr(uart_tx_enable),

8
Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst
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@@ -1,9 +1,9 @@
#IO_LOC "o_tx" 73;
IO_LOC "o_tx" 69;
#IO_LOC "o_tx" 69;
IO_LOC "o_tx" 73;
IO_PORT "o_tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_rx" 70;
#IO_LOC "i_rx" 74;
#IO_LOC "i_rx" 70;
IO_LOC "i_rx" 74;
IO_PORT "i_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_clk" 4;

4
Semaine_7/ESP32/leds_commands/scripts/linux/upload.sh
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@@ -6,7 +6,7 @@ cd "$(dirname "$0")/../.." || exit 1
# Config de base
DEVICE="GW2AR-LV18QN88C8/I7"
BOARD="tangnano20k"
TOP="dht11_uart_top"
TOP="fpga_wifi_led"
CST_FILE="$TOP.cst"
JSON_FILE="runs/$TOP.json"
PNR_JSON="runs/pnr_$TOP.json"
@@ -16,7 +16,7 @@ BITSTREAM="runs/$TOP.fs"
mkdir -p runs
echo "=== Étape 4 : Flash avec openFPGALoader ==="
sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
sudo /home/louis/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
if [ $? -ne 0 ]; then
echo "=== Erreur lors du flash ==="
exit 1

4
Semaine_7/ESP32/leds_commands/src/esp32/wifi_esp32/wifi_esp32.ino
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@@ -20,11 +20,11 @@ bool touchDetected = false;
// UART pins for FPGA communication
const int UART_RX_PIN = 16; // GPIO16 - RX from FPGA
const int UART_TX_PIN = 17; // GPIO17 - TX to FPGA
const int UART_BAUD = 115200;
const int UART_BAUD = 3000000;
void setup() {
// Initialize Serial for USB debugging (115200 baud)
Serial.begin(115200);
Serial.begin(115200);
// Initialize Serial2 for FPGA communication
Serial2.begin(UART_BAUD, SERIAL_8N1, UART_RX_PIN, UART_TX_PIN);

49
Semaine_7/ESP32/leds_commands/src/verilog/fpga_wifi_led.v
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@@ -5,13 +5,30 @@ module fpga_wifi_led (
output o_tx,
output [5:0] o_leds
);
// === PARAMÈTRES ===
localparam CLK_FREQ = 27_000_000; //57_857_142;
localparam BAUD_RATE = 115200;
localparam CLK_FREQ = 57_857_142;//27_000_000;
localparam BAUD_RATE = 3_000_000;
localparam FIFO_SIZE = 8;
wire out_clk, clk_lock;
rPLL #( // For GW1NR-9C C6/I5 (Tang Nano 9K proto dev board)
.FCLKIN("27"),
.IDIV_SEL(6), // -> PFD = 3.857142857142857 MHz (range: 3-400 MHz)
.FBDIV_SEL(14), // -> CLKOUT = 57.857142857142854 MHz (range: 3.125-600 MHz)
.ODIV_SEL(16) // -> VCO = 925.7142857142857 MHz (range: 400-1200 MHz)
) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0),
.CLKIN(i_clk), // 27 MHz
.CLKOUT(out_clk), // 57.857142857142854 MHz
.LOCK(clk_lock)
);
//assign out_clk = i_clk;
// === SIGNAUX UART RX ===
wire [7:0] rx_data;
wire rx_data_available;
@@ -27,24 +44,6 @@ module fpga_wifi_led (
reg [1:0] state;
reg [7:0] received_byte;
wire out_clk;
wire clk_lock;
/*
rPLL #( // For GW1NR-9C C6/I5 (Tang Nano 9K proto dev board)
.FCLKIN("27"),
.IDIV_SEL(6), // -> PFD = 3.857142857142857 MHz (range: 3-400 MHz)
.FBDIV_SEL(14), // -> CLKOUT = 50.142857142857146 MHz (range: 3.125-600 MHz)
.ODIV_SEL(16) // -> VCO = 401.14285714285717 MHz (range: 400-1200 MHz)
) pll (.CLKOUTP(), .CLKOUTD(), .CLKOUTD3(), .RESET(1'b0), .RESET_P(1'b0), .CLKFB(1'b0), .FBDSEL(6'b0), .IDSEL(6'b0), .ODSEL(6'b0), .PSDA(4'b0), .DUTYDA(4'b0), .FDLY(4'b0),
.CLKIN(i_clk), // 27 MHz
.CLKOUT(out_clk), // 50.142857142857146 MHz
.LOCK(clk_lock)
);
*/
assign out_clk = i_clk;
// === ÉTATS DE LA FSM ===
localparam IDLE = 2'd0,
WAIT_BYTE = 2'd1,
@@ -101,7 +100,7 @@ module fpga_wifi_led (
case (state)
IDLE: begin
received_byte <= 8'h00;
leds_reg[2:0] <= 3'b100;
if (rx_data_available) begin
state <= WAIT_BYTE;
end
@@ -117,13 +116,13 @@ module fpga_wifi_led (
PROCESS_CMD: begin
// Vérifier la commande reçue
if (received_byte == 8'h01) begin
if (received_byte == 8'h31) begin
// Allumer la LED 0
leds_reg[0] <= 1;
// Préparer la réponse
state <= SEND_RESPONSE;
end else if (received_byte == 8'h02) begin
end else if (received_byte == 8'h32) begin
// Éteindre la LED 0
leds_reg[0] <= 0;
@@ -132,7 +131,7 @@ module fpga_wifi_led (
end else begin
// Commande non reconnue, éteindre toutes les LEDs
leds_reg[2:0] <= 3'b111;
state <= IDLE;
state <= SEND_RESPONSE; //IDLE;
end
end

4
Semaine_7/ESP32/leds_commands/tests/pyhton/connectESP.py
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@@ -2,7 +2,7 @@ import socket
import time
# Remplace cette IP par celle affichée par l'ESP32 dans le terminal série
ESP32_IP = "172.20.10.13"
ESP32_IP = "192.168.1.107"
ESP32_PORT = 1234
def send_bytes(commands):
@@ -24,5 +24,5 @@ def send_bytes(commands):
print("Erreur :", e)
# Exemple d'envoi
commands = [0x01]
commands = [0x31] # Tu peux aussi faire ["0x01", "0x96", "0xA4"]
send_bytes(commands)