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FPGA_ESP32_WIFI_Fonctionnel 3MB

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Louis TANCHOU
2025-06-03 09:04:26 +02:00
parent 3541476e9a
commit 20cbaace08
8 changed files with 49 additions and 38 deletions
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2
Semaine_7/ESP32/leds_commands/IP/verilog/rxuartlite.v
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@@ -52,7 +52,7 @@ module rxuartlite #(
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 27MHz
`endif
localparam TB = TIMER_BITS,
//

9
Semaine_7/ESP32/leds_commands/IP/verilog/uart_rx_fifo.v
View File

@@ -19,8 +19,15 @@ module uart_rx_fifo #(
wire fifo_empty;
wire fifo_full;
localparam integer CPB = CLK_FREQ/BAUD_RATE;
// UART Receiver instance
rxuartlite uart_rx_inst (
rxuartlite
#(
.CLOCKS_PER_BAUD(CPB),
.TIMER_BITS($clog2(CPB)+1)
) uart_rx_inst
(
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),

7
Semaine_7/ESP32/leds_commands/IP/verilog/uart_tx_fifo.v
View File

@@ -45,7 +45,12 @@ module uart_tx_fifo #(
);
// UART TX instantiation
txuartlite uart_tx_inst (
txuartlite
#(
.CLOCKS_PER_BAUD(CLK_FREQ/BAUD_RATE),
.TIMING_BITS($clog2(CLK_FREQ/BAUD_RATE)+1)
) uart_tx_inst
(
.i_clk(clk),
.i_reset(1'b0),
.i_wr(uart_tx_enable),