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FPGA_ESP32_WIFI_Fonctionnel 3MB

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Louis TANCHOU
2025-06-03 09:04:26 +02:00
parent 3541476e9a
commit 20cbaace08
8 changed files with 49 additions and 38 deletions
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Semaine_7/ESP32/leds_commands/IP/verilog/rxuartlite.v
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@@ -52,7 +52,7 @@ module rxuartlite #(
`ifdef FORMAL
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 16, // Necessary for formal proof
`else
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 100MHz
parameter [(TIMER_BITS-1):0] CLOCKS_PER_BAUD = 234, // 115200 Baud at 27MHz
`endif
localparam TB = TIMER_BITS,
//