verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

FPGA_ESP32_WIFI_Fonctionnel 3MB

Browse Source
This commit is contained in:
Louis TANCHOU
2025-06-03 09:04:26 +02:00
parent 3541476e9a
commit 20cbaace08
8 changed files with 49 additions and 38 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Semaine_7/ESP32/leds_commands/constraints/fpga_wifi_led.cst
View File

@@ -1,9 +1,9 @@
#IO_LOC "o_tx" 73;
IO_LOC "o_tx" 69;
#IO_LOC "o_tx" 69;
IO_LOC "o_tx" 73;
IO_PORT "o_tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_rx" 70;
#IO_LOC "i_rx" 74;
#IO_LOC "i_rx" 70;
IO_LOC "i_rx" 74;
IO_PORT "i_rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "i_clk" 4;