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ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer

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This commit is contained in:
Gamenight77
2025-05-12 12:15:52 +02:00
parent 004def5ba2
commit 30bbe27510
16 changed files with 1273 additions and 171 deletions
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12
Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst
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@@ -7,3 +7,15 @@ IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "sig" 73;
IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

14
Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
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@@ -2,6 +2,7 @@ module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
output reg [5:0] leds
);
@@ -43,7 +44,7 @@ module top_uart_ultrason (
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine
leds <= distance[7:2];
start <= 1;
case (state)
@@ -63,16 +64,7 @@ module top_uart_ultrason (
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE;
delay_counter <= 0;
end
state <= IDLE;
end
endcase

6
Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py
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@@ -1,9 +1,9 @@
import serial
# === Configuration ===
PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux)
BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo
TIMEOUT = 1 # En secondes
PORT = 'COM6'
BAUDRATE = 115200
TIMEOUT = 1
# === Connexion série ===
ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT)