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ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer

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This commit is contained in:
Gamenight77
2025-05-12 12:15:52 +02:00
parent 004def5ba2
commit 30bbe27510
16 changed files with 1273 additions and 171 deletions
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14
Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
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@@ -2,6 +2,7 @@ module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
output reg [5:0] leds
);
@@ -43,7 +44,7 @@ module top_uart_ultrason (
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine
leds <= distance[7:2];
start <= 1;
case (state)
@@ -63,16 +64,7 @@ module top_uart_ultrason (
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE;
delay_counter <= 0;
end
state <= IDLE;
end
endcase