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ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer

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This commit is contained in:
Gamenight77
2025-05-12 12:15:52 +02:00
parent 004def5ba2
commit 30bbe27510
16 changed files with 1273 additions and 171 deletions
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18
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
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@@ -1,25 +1,24 @@
module fifo #(
parameter DEPTH = 16,
parameter SIZE = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
output wire[WIDTH-1:0] rd_data,
output reg[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DEPTH-1];
reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
assign full = (count == DEPTH);
assign full = (count == SIZE);
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
@@ -27,15 +26,16 @@
count = 0;
end
always @(posedge clk) begin
always @(posedge clk) begin // IN
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % DEPTH;
wr_ptr <= (wr_ptr + 1) % SIZE;
count <= count + 1;
end
if (rd_en && !empty) begin
rd_ptr <= (rd_ptr + 1) % DEPTH;
if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
count <= count - 1;
end
end

796
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/rxuartlite.v Normal file
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File diff suppressed because it is too large Load Diff

64
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v Normal file
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@@ -0,0 +1,64 @@
module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_SIZE = 8
)(
input clk,
input rd_en,
output reg [7:0] rd_data,
input rx_pin,
output data_available
);
// UART RX wires
wire [7:0] rx_data;
wire rx_received;
// FIFO control
reg wr_en;
wire fifo_empty;
wire fifo_full;
wire [7:0] fifo_rd_data;
// UART Receiver instance
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),
.o_wr(rx_received),
.o_data(rx_data)
);
// FIFO instance
fifo #(
.WIDTH(8),
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign data_available = ~fifo_empty;
// Enregistrement explicite des données lues pour stabilité
always @(posedge clk) begin
if (rd_en && !fifo_empty) begin
rd_data <= fifo_rd_data;
end
end
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
wr_en <= 1'b1;
end else begin
wr_en <= 1'b0;
end
end
endmodule

4
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
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@@ -1,7 +1,7 @@
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input wr_en,
@@ -32,7 +32,7 @@ module uart_tx_fifo #(
// FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),

95
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_sensor.v Normal file
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@@ -0,0 +1,95 @@
module ultrasonic_sensor( // Simulation of an ultrasonic sensor
input wire clk,
inout wire signal // Signal from the ultrasonic sensor
);
parameter integer CLK_FREQ = 27_000_000;
reg [2:0] state = 3'd0; // State of the FSM
reg [2:0] next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter = 0; // Counter for the trigger pulse
reg [31:0] echo_counter = 0; // Echo signal
reg valid_trig = 0; // Valid trigger signal
reg echo_sended = 0; // Flag to indicate if echo has been sent
reg signal_out = 0;
assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
localparam S_WAIT_TRIG = 3'd0,
S_MEASURE_TRIG = 3'd1,
S_SEND_ECHO = 3'd2;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
always @(*) begin
case (state)
S_WAIT_TRIG: begin
sig_dir = 0;
if (signal == 1) begin
next_state = S_MEASURE_TRIG;
end else begin
next_state = S_WAIT_TRIG;
end
end
S_MEASURE_TRIG: begin
sig_dir = 0;
if (valid_trig)begin
next_state = S_SEND_ECHO;
end
end
S_SEND_ECHO: begin
sig_dir = 1; // Mettre en sortie
if (echo_sended) begin
echo_sended = 0; // Reset flag
next_state = S_WAIT_TRIG;
end else begin
next_state = S_SEND_ECHO;
end
end
default: begin
sig_dir = 0;
next_state = S_WAIT_TRIG;
end
endcase
end
always @(posedge clk) begin
state <= next_state;
end
always @(posedge clk) begin
if (state == S_MEASURE_TRIG) begin
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES-20) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;
end
end
end
end
reg [15:0] echo_delay_counter;
always @(posedge clk) begin
if (state == S_SEND_ECHO) begin
if (echo_delay_counter == 5800) begin //
signal_out <= 0;
echo_sended <= 1;
end else begin
signal_out <= 1;
echo_delay_counter <= echo_delay_counter + 1;
end
end else begin
echo_delay_counter <= 0;
end
end
endmodule