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ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer

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This commit is contained in:
Gamenight77
2025-05-12 12:15:52 +02:00
parent 004def5ba2
commit 30bbe27510
16 changed files with 1273 additions and 171 deletions
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81
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v
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module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
);
// === UART TX WIRE ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// === UART TX FIFO ===
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.fifo_full(tx_fifo_full),
.tx_pin(tx)
);
// === Ultrasonic ===
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
) ultrasonic_inst (
.clk(clk),
.start(start),
.sig(sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(done)
);
// === FSM ===
localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3;
reg [1:0] state = IDLE;
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine
start <= 1;
case (state)
IDLE: begin
wr_en <= 0;
if (done) begin
state <= SEND_LOW;
wr_en <= 1;
end
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE;
delay_counter <= 0;
end
end
endcase
end
endmodule

175
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v Normal file
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module top_uart_ultrason_command (
input wire clk, // 27 MHz
output wire tx,
input wire rx,
inout wire ultrason_sig, // Capteur ultrason
output reg [5:0] leds
);
// === UART RX WIRE ===
wire [7:0] rd_data;
reg rd_en = 0;
wire data_available;
// RX FIFO Instance
uart_rx_fifo uart_rx_inst (
.clk(clk),
.rx_pin(rx),
.rd_data(rd_data),
.rd_en(rd_en),
.data_available(data_available)
);
// === UART TX WIRE ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// === UART TX FIFO ===
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.fifo_full(tx_fifo_full),
.tx_pin(tx)
);
// === Ultrasonic ===
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
) ultrasonic_inst (
.clk(clk),
.start(start),
.sig(ultrason_sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(done)
);
// === FSM ===
localparam IDLE = 0, READ = 1;
localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
reg [1:0] rx_state = IDLE;
reg [1:0] command = 0;
reg [8:0] delay_counter = 0;
localparam MESURE = 1, SEND_LOW = 2, SEND_HIGH = 3, WAIT = 4;
reg [1:0] tx_state = MESURE;
reg [1:0] mesure = STOP;
always @(posedge clk) begin
leds [5] <= rx;
leds [4] <= tx;
case (rx_state)
IDLE: begin
wr_en <= 0;
rd_en <= 0;
if (data_available && !tx_fifo_full) begin
rd_en <= 1'b1;
rx_state <= READ;
end else begin
rx_state <= IDLE;
end
end
READ: begin
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;
mesure <= ONE;
rx_state <= IDLE;
end
8'h02: begin // Start mesure continuous mesure
start <= 1;
mesure <= CONTINUOUS;
rx_state <= IDLE;
end
8'h03: begin // Stop mesure
start <= 0;
mesure <= STOP;
rx_state <= IDLE;
end
default: begin
mesure <= STOP;
rx_state <= IDLE;
end
endcase
end
endcase
end
// Mesure block
always @(posedge clk) begin
leds <= mesure[1:0];
case (tx_state)
MESURE: begin
case (mesure)
STOP: begin // Stop mesure
start <= 0;
end
ONE: begin // One mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
end else begin
tx_state <= MESURE;
mesure <= STOP;
end
end
CONTINUOUS: begin // Continuous mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
end else begin
tx_state <= IDLE;
end
end
default:
start <= 0;
endcase
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
tx_state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
tx_state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
tx_state <= MESURE;
delay_counter <= 0;
end
wr_en <= 0;
end
default:
tx_state <= MESURE;
endcase
end
endmodule