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ultrasonic commands commencer et tester mais non fonctionnel donc début de testbench pour pouvoir debuguer

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This commit is contained in:
Gamenight77
2025-05-12 12:15:52 +02:00
parent 004def5ba2
commit 30bbe27510
16 changed files with 1273 additions and 171 deletions
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12
Semaine_4/UART_ULTRASON/constraints/top_uart_ultrason.cst
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@@ -7,3 +7,15 @@ IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "sig" 73;
IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

12
Semaine_4/UART_ULTRASON/src/verilog/top_uart_ultrason.v
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@@ -2,6 +2,7 @@ module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
output reg [5:0] leds
);
@@ -43,7 +44,7 @@ module top_uart_ultrason (
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine
leds <= distance[7:2];
start <= 1;
case (state)
@@ -63,16 +64,7 @@ module top_uart_ultrason (
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE;
delay_counter <= 0;
end
end
endcase

6
Semaine_4/UART_ULTRASON/tests/Python/uart_ultrason_receiver.py
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@@ -1,9 +1,9 @@
import serial
# === Configuration ===
PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux)
BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo
TIMEOUT = 1 # En secondes
PORT = 'COM6'
BAUDRATE = 115200
TIMEOUT = 1
# === Connexion série ===
ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT)

18
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/fifo.v
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@@ -1,25 +1,24 @@
module fifo #(
parameter DEPTH = 16,
parameter SIZE = 16,
parameter WIDTH = 8
)(
input wire clk,
input wire wr_en,
input wire[WIDTH-1:0] wr_data,
input wire rd_en,
output wire[WIDTH-1:0] rd_data,
output reg[WIDTH-1:0] rd_data,
output wire full,
output wire empty
);
reg [WIDTH-1:0] fifo[0:DEPTH-1];
reg [WIDTH-1:0] fifo[0:SIZE-1];
reg [3:0] wr_ptr;
reg [3:0] rd_ptr;
reg [3:0] count;
assign full = (count == DEPTH);
assign full = (count == SIZE);
assign empty = (count == 0);
assign rd_data = fifo[rd_ptr];
initial begin
wr_ptr = 0;
@@ -27,15 +26,16 @@
count = 0;
end
always @(posedge clk) begin
always @(posedge clk) begin // IN
if (wr_en && !full) begin
fifo[wr_ptr] <= wr_data;
wr_ptr <= (wr_ptr + 1) % DEPTH;
wr_ptr <= (wr_ptr + 1) % SIZE;
count <= count + 1;
end
if (rd_en && !empty) begin
rd_ptr <= (rd_ptr + 1) % DEPTH;
if (rd_en && !empty) begin // OUT
rd_ptr <= (rd_ptr + 1) % SIZE;
rd_data <= fifo[rd_ptr];
count <= count - 1;
end
end

796
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/rxuartlite.v Normal file
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File diff suppressed because it is too large Load Diff

64
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_rx_fifo.v Normal file
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@@ -0,0 +1,64 @@
module uart_rx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_SIZE = 8
)(
input clk,
input rd_en,
output reg [7:0] rd_data,
input rx_pin,
output data_available
);
// UART RX wires
wire [7:0] rx_data;
wire rx_received;
// FIFO control
reg wr_en;
wire fifo_empty;
wire fifo_full;
wire [7:0] fifo_rd_data;
// UART Receiver instance
rxuartlite uart_rx_inst (
.i_clk(clk),
.i_reset(1'b0),
.i_uart_rx(rx_pin),
.o_wr(rx_received),
.o_data(rx_data)
);
// FIFO instance
fifo #(
.WIDTH(8),
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(rx_data),
.rd_en(rd_en),
.rd_data(fifo_rd_data),
.empty(fifo_empty),
.full(fifo_full)
);
assign data_available = ~fifo_empty;
// Enregistrement explicite des données lues pour stabilité
always @(posedge clk) begin
if (rd_en && !fifo_empty) begin
rd_data <= fifo_rd_data;
end
end
// Écriture dans la FIFO uniquement si donnée reçue ET FIFO pas pleine
always @(posedge clk) begin
if (rx_received && !fifo_full) begin
wr_en <= 1'b1;
end else begin
wr_en <= 1'b0;
end
end
endmodule

4
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/uart_tx_fifo.v
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@@ -1,7 +1,7 @@
module uart_tx_fifo #(
parameter CLK_FREQ = 27_000_000,
parameter BAUD_RATE = 115200,
parameter FIFO_DEPTH = 8
parameter FIFO_SIZE = 8
)(
input clk,
input wr_en,
@@ -32,7 +32,7 @@ module uart_tx_fifo #(
// FIFO instantiation
fifo #(
.WIDTH(8),
.DEPTH(FIFO_DEPTH)
.SIZE(FIFO_SIZE)
) fifo_inst (
.clk(clk),
.wr_en(wr_en),

95
Semaine_5/UART_ULTRASON_COMMANDS/IP/verilog/ultrasonic_sensor.v Normal file
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@@ -0,0 +1,95 @@
module ultrasonic_sensor( // Simulation of an ultrasonic sensor
input wire clk,
inout wire signal // Signal from the ultrasonic sensor
);
parameter integer CLK_FREQ = 27_000_000;
reg [2:0] state = 3'd0; // State of the FSM
reg [2:0] next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter = 0; // Counter for the trigger pulse
reg [31:0] echo_counter = 0; // Echo signal
reg valid_trig = 0; // Valid trigger signal
reg echo_sended = 0; // Flag to indicate if echo has been sent
reg signal_out = 0;
assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
localparam S_WAIT_TRIG = 3'd0,
S_MEASURE_TRIG = 3'd1,
S_SEND_ECHO = 3'd2;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
always @(*) begin
case (state)
S_WAIT_TRIG: begin
sig_dir = 0;
if (signal == 1) begin
next_state = S_MEASURE_TRIG;
end else begin
next_state = S_WAIT_TRIG;
end
end
S_MEASURE_TRIG: begin
sig_dir = 0;
if (valid_trig)begin
next_state = S_SEND_ECHO;
end
end
S_SEND_ECHO: begin
sig_dir = 1; // Mettre en sortie
if (echo_sended) begin
echo_sended = 0; // Reset flag
next_state = S_WAIT_TRIG;
end else begin
next_state = S_SEND_ECHO;
end
end
default: begin
sig_dir = 0;
next_state = S_WAIT_TRIG;
end
endcase
end
always @(posedge clk) begin
state <= next_state;
end
always @(posedge clk) begin
if (state == S_MEASURE_TRIG) begin
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES-20) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;
end
end
end
end
reg [15:0] echo_delay_counter;
always @(posedge clk) begin
if (state == S_SEND_ECHO) begin
if (echo_delay_counter == 5800) begin //
signal_out <= 0;
echo_sended <= 1;
end else begin
signal_out <= 1;
echo_delay_counter <= echo_delay_counter + 1;
end
end else begin
echo_delay_counter <= 0;
end
end
endmodule

9
Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason.cst
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@@ -1,9 +0,0 @@
IO_LOC "tx" 69;
IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "sig" 73;
IO_PORT "sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;

24
Semaine_5/UART_ULTRASON_COMMANDS/constraints/top_uart_ultrason_command.cst Normal file
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@@ -0,0 +1,24 @@
IO_LOC "tx" 69;
IO_PORT "tx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "rx" 70;
IO_PORT "rx" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "clk" 4;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;
IO_LOC "ultrason_sig" 73;
IO_PORT "ultrason_sig" IO_TYPE=LVCMOS33 PULL_MODE=UP DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "leds[0]" 15;
IO_PORT "leds[0]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[1]" 16;
IO_PORT "leds[1]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[2]" 17;
IO_PORT "leds[2]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[3]" 18;
IO_PORT "leds[3]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[4]" 19;
IO_PORT "leds[4]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;
IO_LOC "leds[5]" 20;
IO_PORT "leds[5]" PULL_MODE=UP DRIVE=8 BANK_VCCIO=1.8;

4
Semaine_5/UART_ULTRASON_COMMANDS/scripts/build.bat
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@@ -7,7 +7,7 @@ cd /d %~dp0\..
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
set TOP=top_uart_ultrason
set TOP=top_uart_ultrason_command
set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json
@@ -19,7 +19,7 @@ if not exist runs (
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

81
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason.v
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@@ -1,81 +0,0 @@
module top_uart_ultrason (
input wire clk, // 27 MHz
output wire tx,
inout wire sig, // Capteur ultrason
);
// === UART TX WIRE ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// === UART TX FIFO ===
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.fifo_full(tx_fifo_full),
.tx_pin(tx)
);
// === Ultrasonic ===
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
) ultrasonic_inst (
.clk(clk),
.start(start),
.sig(sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(done)
);
// === FSM ===
localparam IDLE = 0, WAIT = 1 ,SEND_LOW = 2, SEND_HIGH = 3;
reg [1:0] state = IDLE;
reg [8:0] delay_counter = 0;
always @(posedge clk) begin
// Activer en continu tant que FIFO pas pleine
start <= 1;
case (state)
IDLE: begin
wr_en <= 0;
if (done) begin
state <= SEND_LOW;
wr_en <= 1;
end
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
state <= IDLE;
delay_counter <= 0;
end
end
endcase
end
endmodule

175
Semaine_5/UART_ULTRASON_COMMANDS/src/verilog/top_uart_ultrason_command.v Normal file
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@@ -0,0 +1,175 @@
module top_uart_ultrason_command (
input wire clk, // 27 MHz
output wire tx,
input wire rx,
inout wire ultrason_sig, // Capteur ultrason
output reg [5:0] leds
);
// === UART RX WIRE ===
wire [7:0] rd_data;
reg rd_en = 0;
wire data_available;
// RX FIFO Instance
uart_rx_fifo uart_rx_inst (
.clk(clk),
.rx_pin(rx),
.rd_data(rd_data),
.rd_en(rd_en),
.data_available(data_available)
);
// === UART TX WIRE ===
reg [7:0] wr_data;
reg wr_en;
wire tx_fifo_full;
// === UART TX FIFO ===
uart_tx_fifo uart_tx_inst (
.clk(clk),
.wr_en(wr_en),
.wr_data(wr_data),
.fifo_full(tx_fifo_full),
.tx_pin(tx)
);
// === Ultrasonic ===
reg start = 0;
wire ultrasonic_busy;
wire [15:0] distance;
wire done;
ultrasonic_fpga #(
.CLK_FREQ(27_000_000)
) ultrasonic_inst (
.clk(clk),
.start(start),
.sig(ultrason_sig),
.distance(distance),
.busy(ultrasonic_busy),
.done(done)
);
// === FSM ===
localparam IDLE = 0, READ = 1;
localparam STOP = 3, ONE = 1, CONTINUOUS = 2;
reg [1:0] rx_state = IDLE;
reg [1:0] command = 0;
reg [8:0] delay_counter = 0;
localparam MESURE = 1, SEND_LOW = 2, SEND_HIGH = 3, WAIT = 4;
reg [1:0] tx_state = MESURE;
reg [1:0] mesure = STOP;
always @(posedge clk) begin
leds [5] <= rx;
leds [4] <= tx;
case (rx_state)
IDLE: begin
wr_en <= 0;
rd_en <= 0;
if (data_available && !tx_fifo_full) begin
rd_en <= 1'b1;
rx_state <= READ;
end else begin
rx_state <= IDLE;
end
end
READ: begin
case (rd_data)
8'h01: begin // Start mesure one mesure
start <= 1;
mesure <= ONE;
rx_state <= IDLE;
end
8'h02: begin // Start mesure continuous mesure
start <= 1;
mesure <= CONTINUOUS;
rx_state <= IDLE;
end
8'h03: begin // Stop mesure
start <= 0;
mesure <= STOP;
rx_state <= IDLE;
end
default: begin
mesure <= STOP;
rx_state <= IDLE;
end
endcase
end
endcase
end
// Mesure block
always @(posedge clk) begin
leds <= mesure[1:0];
case (tx_state)
MESURE: begin
case (mesure)
STOP: begin // Stop mesure
start <= 0;
end
ONE: begin // One mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
end else begin
tx_state <= MESURE;
mesure <= STOP;
end
end
CONTINUOUS: begin // Continuous mesure
start <= 1;
if (done) begin
tx_state <= SEND_LOW;
wr_en <= 1;
end else begin
tx_state <= IDLE;
end
end
default:
start <= 0;
endcase
end
SEND_LOW: begin
wr_en <= 1;
wr_data <= distance[7:0]; // Octet LSB
tx_state <= SEND_HIGH;
end
SEND_HIGH: begin
wr_data <= distance[15:8]; // Octet MSB
tx_state <= WAIT;
end
WAIT: begin // Code non testé
if (delay_counter < 1000000) begin
delay_counter <= delay_counter + 1;
end else begin
tx_state <= MESURE;
delay_counter <= 0;
end
wr_en <= 0;
end
default:
tx_state <= MESURE;
endcase
end
endmodule

21
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/uart_ultrason_receiver.py
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@@ -1,21 +0,0 @@
import serial
# === Configuration ===
PORT = 'COM7' # Remplace par le port série de ton FPGA (ex: '/dev/ttyUSB0' sur Linux)
BAUDRATE = 115200 # À adapter selon ton uart_tx_fifo
TIMEOUT = 1 # En secondes
# === Connexion série ===
ser = serial.Serial(PORT, BAUDRATE, timeout=TIMEOUT)
print(f"Ouvert sur {PORT} à {BAUDRATE} bauds.")
try:
while True:
data = ser.read(1) # Lire 1 octet
if data:
value = int.from_bytes(data, byteorder='little')
print(f"Distance mesurée : {value} cm")
except KeyboardInterrupt:
print("\nArrêté par l'utilisateur.")
finally:
ser.close()

68
Semaine_5/UART_ULTRASON_COMMANDS/tests/Python/ultrason_command.py Normal file
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@@ -0,0 +1,68 @@
import serial
import time
import struct
# === Paramètres de communication ===
SERIAL_PORT = "COM6" # Modifie selon ton système, ex. "/dev/ttyUSB0" sur Linux
BAUDRATE = 115200 # Change si différent
TIMEOUT = 2 # secondes
# === Commandes (doivent correspondre aux valeurs Verilog) ===
CMD_STOP = 3
CMD_ONE = 1
CMD_CONTINUOUS = 2
def send_command(ser, command):
"""Envoie une commande au FPGA"""
ser.write(bytes([command]))
def read_distance(ser):
"""Lit 2 octets et les convertit en distance (int16)"""
data = ser.read(2)
if len(data) != 2:
return None
# Interprétation little-endian (LSB, MSB)
lsb, msb = data[0], data[1]
distance = msb << 8 | lsb
return distance
def main():
with serial.Serial(SERIAL_PORT, BAUDRATE, timeout=TIMEOUT) as ser:
print("Connexion ouverte sur", SERIAL_PORT)
mode = input("Mode (one / continuous / stop) ? ").strip().lower()
if mode == "one":
send_command(ser, CMD_ONE)
print("Mesure unique demandée. Attente résultat...")
time.sleep(0.05)
distance = read_distance(ser)
if distance is not None:
print(f"Distance mesurée : {distance} cm")
else:
print("Erreur : distance non reçue.")
elif mode == "continuous":
send_command(ser, CMD_CONTINUOUS)
print("Mesures continues (CTRL+C pour stopper) :")
try:
while True:
distance = read_distance(ser)
if distance is not None:
print(f"Distance : {distance} cm")
else:
print("... (aucune donnée reçue)")
time.sleep(0.1)
except KeyboardInterrupt:
send_command(ser, CMD_STOP)
print("\nMesure continue arrêtée.")
elif mode == "stop":
send_command(ser, CMD_STOP)
print("Commande STOP envoyée.")
else:
print("Commande invalide.")
if __name__ == "__main__":
main()

51
Semaine_5/UART_ULTRASON_COMMANDS/tests/verilog/tb_uart_ultrason.v
View File

@@ -1,6 +1,6 @@
`timescale 1ns/1ps
module tb_uart;
module tb_ultrason_commands;
reg clk = 0;
reg tx_enable = 0;
@@ -11,19 +11,32 @@ module tb_uart;
reg rx_received;
wire rx_enable = 1'b1;
wire pin;
wire rx,tx;
always #18.5 clk = ~clk;
localparam CLK_FREQ = 27_000_000;
localparam BAUD_RATE = 115_200;
ultrasonic_sensor ultrasonic_sensor_instance (
.clk(clk),
.signal(ultrason_sig)
);
top_uart_ultrason_command top_uart_ultrason_command_instance (
.clk(clk),
.rx(rx),
.tx(tx),
.ultrason_sig(ultrason_sig),
.leds()
);
uart_rx #(
.CLK_FREQ(CLK_FREQ),
.BAUD_RATE(BAUD_RATE)
) rx_instance (
.clk(clk),
.rx_pin(pin),
.rx_pin(tx),
.rx_data(data_out),
.rx_received(rx_received),
.rx_enable(rx_enable)
@@ -37,7 +50,7 @@ module tb_uart;
.tx_enable(tx_enable),
.tx_ready(tx_ready),
.data(data_in),
.tx(pin),
.tx(rx),
.rst_p(1'b0)
);
@@ -45,37 +58,11 @@ module tb_uart;
$dumpfile("runs/uart.vcd");
$dumpvars(0, tb_uart);
$display("======== Start UART LOOPBACK test =========");
$display("======== Start UART ULTRASONIC COMMANDS =========");
#100;
data_in <= 8'd234; // 234
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
#1000;
wait(tx_ready == 1'b1); // Attendre que le signal de reception soit actif
data_in <= 8'd202; // 202
tx_enable <= 1;
wait(tx_ready == 1'b0);
tx_enable <= 0;
// Attendre
wait (rx_received == 1'b1); // Attendre que le signal de reception soit actif
$display("Data received: %d", data_out); // Afficher la valeur recu
$display("Data expected: %d", data_in); // Afficher la valeur envoyee
$display("======== END UART TX test =========");
$display("======== END UART ULTRASONIC COMMANDS =========");
#1000;
$stop;