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vLundi juin

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This commit is contained in:
Louis TANCHOU
2025-06-02 14:42:40 +02:00
parent 3f3e4fcd6b
commit 3541476e9a
6 changed files with 16 additions and 11 deletions
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6
Semaine_7/ESP32/leds_commands/scripts/linux/build.sh
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@@ -6,7 +6,7 @@ cd "$(dirname "$0")/../.." || exit 1
# Config de base
DEVICE="GW2AR-LV18QN88C8/I7"
BOARD="tangnano20k"
TOP="dht11_uart_top"
TOP="fpga_wifi_led"
CST_FILE="$TOP.cst"
JSON_FILE="runs/$TOP.json"
PNR_JSON="runs/pnr_$TOP.json"
@@ -16,7 +16,7 @@ BITSTREAM="runs/$TOP.fs"
mkdir -p runs
echo "=== Étape 1 : Synthèse avec Yosys ==="
yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top $TOP -json $JSON_FILE"
yosys -p "read_verilog -sv src/verilog/$TOP.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v IP/verilog/rxuartlite.v; synth_gowin -top $TOP -json $JSON_FILE"
if [ $? -ne 0 ]; then
echo "=== Erreur lors de la synthèse ==="
exit 1
@@ -37,7 +37,7 @@ if [ $? -ne 0 ]; then
fi
echo "=== Étape 4 : Flash avec openFPGALoader ==="
sudo /etc/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
sudo /home/louis/oss-cad-suite/bin/openFPGALoader -b "$BOARD" "$BITSTREAM"
if [ $? -ne 0 ]; then
echo "=== Erreur lors du flash ==="
exit 1