verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

recodage de lundi

Browse Source
This commit is contained in:
Gamenight77
2025-05-27 10:12:31 +02:00
parent 92144d315e
commit 35f84d9d16
3 changed files with 81 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
Semaine_7/DHT11_UART/scripts/windows/build.bat
View File

@@ -2,24 +2,26 @@
setlocal
rem === Aller à la racine du projet ===
cd /d %~dp0\..
cd /d %~dp0\..\..
echo Script lancé depuis : %cd%
rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k
set TOP=top_uart_ultrason_command
set TOP=dht11_uart_top
set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json
set BITSTREAM=runs/%TOP%.fs
rem === Créer le dossier runs si nécessaire ===
if not exist runs (
mkdir runs
if not exist ../runs (
mkdir ../runs
)
echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%"
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===