recodage de lundi

Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v

@@ -16,9 +16,10 @@ wire tx_fifo_full;
 reg i_start;
 wire o_dht11_data_ready;
 wire o_busy;
-wire [7:0] o_temp_data;
-wire [7:0] o_hum_data;
-wire o_dht11_error;
+wire [15:0] o_temp_data;
+wire [15:0] o_hum_data;
+wire [7:0] o_checksum;
+wire [3:0] dht11_state;
 
 uart_tx_fifo #(
     .CLK_FREQ(CLK_FREQ),
@@ -40,16 +41,25 @@ dht11_interface dht11_inst (
     .o_busy(o_busy),
     .o_temp_data(o_temp_data),
     .o_hum_data(o_hum_data),
-    .o_dht11_error(o_dht11_error)
+    .o_checksum(o_checksum),
+    .o_state(dht11_state),
 );
 
 // === FSM ===
-localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3;
-reg [2:0] state = X;
+localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3, SEND_FIFO3 = 5, SEND_FIFO4 = 6;
+reg [3:0] state = X;
 reg [31:0] delay_counter = 0;
 reg strobe2s = 0;
 reg [7:0] data_fifo = 30;
 
+initial begin
+    state = X;
+    i_start = 0;
+    wr_en = 0;
+    wr_data = 0;
+    leds = 6'b000000;
+end
+
 // 2s counter
 always_ff @(posedge clk) begin
     if (delay_counter == CLK_FREQ * 2 - 1) begin
@@ -60,17 +70,17 @@ always_ff @(posedge clk) begin
         strobe2s <= 0;
     end
 
-    leds[5] <= !o_dht11_error;
+    
 end
 
 always_ff @(posedge clk) begin
+    leds <= {dht11_state, 1'b1}; 
     case (state)
         X: begin
             i_start <= 0;
             wr_en <= 1;
             wr_data <= data_fifo;
             state <= WAIT;
-            leds [4:0] = 5'b11110;
         end
         WAIT: begin
             i_start <= 0;
@@ -79,30 +89,39 @@ always_ff @(posedge clk) begin
                 state <= MESURE;
                 i_start <= 1;
             end
-            leds [4:0] = 5'b11100;
         end
 
         MESURE: begin
             i_start <= 0;
             if (o_dht11_data_ready) begin
                 state <= SEND_FIFO1;
-                wr_data <= o_temp_data;
+                wr_data <= o_hum_data[15:8]; // Send temperature MSB
                 wr_en <= 1;
             end
-            leds [4:0] = 5'b11000;
         end
 
         SEND_FIFO1: begin
-            wr_data <= o_hum_data;
+            wr_data <= o_hum_data[7:0]; // Send temperature LSB
             wr_en <= 1;
             state <= SEND_FIFO2;
-            leds [4:0] = 5'b10000;
         end
 
         SEND_FIFO2: begin
-            wr_en <= 0;
+            wr_data <= o_temp_data[15:8]; // Send hum MSB
+            wr_en <= 1;
+            state <= SEND_FIFO3;
+        end
+
+        SEND_FIFO3: begin
+            wr_data <= o_temp_data[7:0]; // Send hum LSB
+            wr_en <= 1;
+            state <= SEND_FIFO4;
+        end
+
+        SEND_FIFO4: begin
+            wr_data <= o_checksum; // Send checksum
+            wr_en <= 1;
             state <= WAIT;
-            leds [4:0] = 5'b00000;
         end
 
         default: state <= WAIT;