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recodage de lundi

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Gamenight77
2025-05-27 10:12:31 +02:00
parent 92144d315e
commit 35f84d9d16
3 changed files with 81 additions and 83 deletions
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103
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -6,41 +6,40 @@ module dht11_interface #(
input wire i_start, input wire i_start,
output reg o_dht11_data_ready, output reg o_dht11_data_ready,
output reg o_busy, output reg o_busy,
output reg [7:0] o_temp_data, output reg [15:0] o_temp_data,
output reg [7:0] o_hum_data, output reg [15:0] o_hum_data,
output reg o_dht11_error output reg [7:0] o_checksum,
output reg [3:0] o_state
); );
// === DHT11 INTERFACE === // === DHT11 INTERFACE ===
// === PARAMÈTRES === // === PARAMÈTRES ===
localparam T_18MS = CLK_FREQ * 18 / 1_000; // cycles pour 18ms a partir localparam T_18MS = CLK_FREQ * 18 / 1_000; // cycles pour 18ms a partir
localparam T_80US = CLK_FREQ * 81 / 1_000_000; localparam T_80US = CLK_FREQ * 90 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000; localparam T_79US = CLK_FREQ * 70 / 1_000_000;
localparam T_71US = CLK_FREQ * 71 / 1_000_000; localparam T_71US = CLK_FREQ * 81 / 1_000_000;
localparam T_51US = CLK_FREQ * 51 / 1_000_000; localparam T_51US = CLK_FREQ * 58 / 1_000_000;
localparam T_50US = CLK_FREQ * 50 / 1_000_000; localparam T_50US = CLK_FREQ * 50 / 1_000_000;
localparam T_49US = CLK_FREQ * 49 / 1_000_000; localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_41US = CLK_FREQ * 41 / 1_000_000; localparam T_41US = CLK_FREQ * 50 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000; localparam T_28US = CLK_FREQ * 32 / 1_000_000;
localparam T_26US = CLK_FREQ * 26 / 1_000_000; localparam T_26US = CLK_FREQ * 25 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000; localparam T_20US = CLK_FREQ * 18 / 1_000_000;
// === Signal bidirectionnel === // === Signal bidirectionnel ===
reg sig_dir; reg sig_dir;
reg sig_out; reg sig_out;
wire sig_in; reg sig_in;
assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz) assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
assign sig_in = io_dht11_sig;
// === REGISTRES === // === REGISTRES ===
reg [3:0] state; reg [3:0] state;
reg [31:0] timer; reg [31:0] timer;
reg [7:0] temp_data, hum_data;
reg [7:0] temp_dec, hum_dec, checksum;
reg [2:0] bit_count; reg [2:0] bit_count;
reg [5:0] bit_index; reg [5:0] bit_index;
reg [39:0] raw_data; reg [39:0] raw_data;
@@ -70,6 +69,7 @@ module dht11_interface #(
// === FSM principale === // === FSM principale ===
always @(posedge i_clk) begin always @(posedge i_clk) begin
sig_in <= io_dht11_sig;
case (state) case (state)
IDLE: begin IDLE: begin
@@ -102,111 +102,88 @@ module dht11_interface #(
end end
WAIT_RESPONSE: begin WAIT_RESPONSE: begin
o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 0) begin if (sig_in == 0) begin
if (timer > T_20US && timer < T_41US) begin
state <= RESPONSE_LOW; state <= RESPONSE_LOW;
timer <= 0; timer <= 0;
end else begin
state <= ERROR;
end
end else if (timer > T_41US) begin
state <= ERROR;
end end
end end
RESPONSE_LOW: begin RESPONSE_LOW: begin
o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 1) begin if (sig_in == 1) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0; timer <= 0;
state <= RESPONSE_HIGH; state <= RESPONSE_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end end
end end
RESPONSE_HIGH: begin RESPONSE_HIGH: begin
timer <= timer + 1; timer <= timer + 1;
o_state <= state;
if (sig_in == 0) begin if (sig_in == 0) begin
if (timer > T_79US && timer < T_80US) begin
timer <= 0; timer <= 0;
state <= READ_BITS_LOW; state <= READ_BITS_LOW;
end else begin
state <= ERROR;
end
end else if (timer > T_80US) begin
state <= ERROR;
end end
end end
READ_BITS_LOW: begin READ_BITS_LOW: begin
o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 1) begin if (sig_in == 1) begin
if (timer > T_49US && timer < T_51US) begin
timer <= 0; timer <= 0;
state <= READ_BITS_HIGH; state <= READ_BITS_HIGH;
end else begin
state <= ERROR;
end
end else if (timer > T_51US) begin
state <= ERROR;
end end
end end
READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1 READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 0) begin if (sig_in == 0) begin
if (timer <= T_26US) begin
state <= ERROR;
end
raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us raw_data <= {raw_data[38:0], (timer > T_28US)}; // 1 si high > ~28us
timer <= 0; timer <= 0;
bit_index <= bit_index + 1; bit_index <= bit_index + 1;
if (bit_index == 39) begin // Code a testé ici pour etre sur de capter le dernier bit if (bit_index == 39) begin
state <= DONE; state <= DONE;
end else begin end else begin
state <= READ_BITS_LOW; state <= READ_BITS_LOW;
end end
end else if (timer > T_71US) begin
state <= ERROR;
end end
end end
DONE: begin DONE: begin
hum_data <= raw_data[39:32]; o_state <= state;
hum_dec <= raw_data[31:24];
temp_data <= raw_data[23:16];
temp_dec <= raw_data[15:8];
checksum <= raw_data[7:0];
if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:32]; o_hum_data <= raw_data[39:24];
o_temp_data <= raw_data[23:16]; o_temp_data <= raw_data[23:8];
o_dht11_data_ready <= 1; o_dht11_data_ready <= 1;
end else begin end
o_dht11_error <= 1;
end o_hum_data <= raw_data[39:24];
o_temp_data <= raw_data[23:8];
o_checksum <= raw_data[7:0];
o_dht11_data_ready <= 1;
o_busy <= 0; o_busy <= 0;
state <= IDLE; state <= IDLE;
end end
ERROR: begin
o_dht11_error <= 1;
state <= IDLE;
end
endcase endcase
end end

12
Semaine_7/DHT11_UART/scripts/windows/build.bat
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@@ -2,24 +2,26 @@
setlocal setlocal
rem === Aller à la racine du projet === rem === Aller à la racine du projet ===
cd /d %~dp0\.. cd /d %~dp0\..\..
echo Script lancé depuis : %cd%
rem === Config de base === rem === Config de base ===
set DEVICE=GW2AR-LV18QN88C8/I7 set DEVICE=GW2AR-LV18QN88C8/I7
set BOARD=tangnano20k set BOARD=tangnano20k
set TOP=top_uart_ultrason_command set TOP=dht11_uart_top
set CST_FILE=%TOP%.cst set CST_FILE=%TOP%.cst
set JSON_FILE=runs/%TOP%.json set JSON_FILE=runs/%TOP%.json
set PNR_JSON=runs/pnr_%TOP%.json set PNR_JSON=runs/pnr_%TOP%.json
set BITSTREAM=runs/%TOP%.fs set BITSTREAM=runs/%TOP%.fs
rem === Créer le dossier runs si nécessaire === rem === Créer le dossier runs si nécessaire ===
if not exist runs ( if not exist ../runs (
mkdir runs mkdir ../runs
) )
echo === Étape 1 : Synthèse avec Yosys === echo === Étape 1 : Synthèse avec Yosys ===
yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/ultrasonic_fpga.v IP/verilog/uart_tx_fifo.v IP/verilog/uart_rx_fifo.v IP/verilog/rxuartlite.v IP/verilog/fifo.v IP/verilog/uart_tx.v; synth_gowin -top %TOP% -json %JSON_FILE%" yosys -p "read_verilog -sv src/verilog/%TOP%.v IP/verilog/dht11_interface.v IP/verilog/uart_tx_fifo.v IP/verilog/fifo.v IP/verilog/txuartlite.v; synth_gowin -top %TOP% -json %JSON_FILE%"
if errorlevel 1 goto error if errorlevel 1 goto error
echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel === echo === Étape 2 : Placement & Routage avec nextpnr-himbaechel ===

49
Semaine_7/DHT11_UART/src/verilog/dht11_uart_top.v
View File

@@ -16,9 +16,10 @@ wire tx_fifo_full;
reg i_start; reg i_start;
wire o_dht11_data_ready; wire o_dht11_data_ready;
wire o_busy; wire o_busy;
wire [7:0] o_temp_data; wire [15:0] o_temp_data;
wire [7:0] o_hum_data; wire [15:0] o_hum_data;
wire o_dht11_error; wire [7:0] o_checksum;
wire [3:0] dht11_state;
uart_tx_fifo #( uart_tx_fifo #(
.CLK_FREQ(CLK_FREQ), .CLK_FREQ(CLK_FREQ),
@@ -40,16 +41,25 @@ dht11_interface dht11_inst (
.o_busy(o_busy), .o_busy(o_busy),
.o_temp_data(o_temp_data), .o_temp_data(o_temp_data),
.o_hum_data(o_hum_data), .o_hum_data(o_hum_data),
.o_dht11_error(o_dht11_error) .o_checksum(o_checksum),
.o_state(dht11_state),
); );
// === FSM === // === FSM ===
localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3; localparam X=4, WAIT = 0, MESURE = 1, SEND_FIFO1 = 2, SEND_FIFO2 = 3, SEND_FIFO3 = 5, SEND_FIFO4 = 6;
reg [2:0] state = X; reg [3:0] state = X;
reg [31:0] delay_counter = 0; reg [31:0] delay_counter = 0;
reg strobe2s = 0; reg strobe2s = 0;
reg [7:0] data_fifo = 30; reg [7:0] data_fifo = 30;
initial begin
state = X;
i_start = 0;
wr_en = 0;
wr_data = 0;
leds = 6'b000000;
end
// 2s counter // 2s counter
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (delay_counter == CLK_FREQ * 2 - 1) begin if (delay_counter == CLK_FREQ * 2 - 1) begin
@@ -60,17 +70,17 @@ always_ff @(posedge clk) begin
strobe2s <= 0; strobe2s <= 0;
end end
leds[5] <= !o_dht11_error;
end end
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
leds <= {dht11_state, 1'b1};
case (state) case (state)
X: begin X: begin
i_start <= 0; i_start <= 0;
wr_en <= 1; wr_en <= 1;
wr_data <= data_fifo; wr_data <= data_fifo;
state <= WAIT; state <= WAIT;
leds [4:0] = 5'b11110;
end end
WAIT: begin WAIT: begin
i_start <= 0; i_start <= 0;
@@ -79,30 +89,39 @@ always_ff @(posedge clk) begin
state <= MESURE; state <= MESURE;
i_start <= 1; i_start <= 1;
end end
leds [4:0] = 5'b11100;
end end
MESURE: begin MESURE: begin
i_start <= 0; i_start <= 0;
if (o_dht11_data_ready) begin if (o_dht11_data_ready) begin
state <= SEND_FIFO1; state <= SEND_FIFO1;
wr_data <= o_temp_data; wr_data <= o_hum_data[15:8]; // Send temperature MSB
wr_en <= 1; wr_en <= 1;
end end
leds [4:0] = 5'b11000;
end end
SEND_FIFO1: begin SEND_FIFO1: begin
wr_data <= o_hum_data; wr_data <= o_hum_data[7:0]; // Send temperature LSB
wr_en <= 1; wr_en <= 1;
state <= SEND_FIFO2; state <= SEND_FIFO2;
leds [4:0] = 5'b10000;
end end
SEND_FIFO2: begin SEND_FIFO2: begin
wr_en <= 0; wr_data <= o_temp_data[15:8]; // Send hum MSB
wr_en <= 1;
state <= SEND_FIFO3;
end
SEND_FIFO3: begin
wr_data <= o_temp_data[7:0]; // Send hum LSB
wr_en <= 1;
state <= SEND_FIFO4;
end
SEND_FIFO4: begin
wr_data <= o_checksum; // Send checksum
wr_en <= 1;
state <= WAIT; state <= WAIT;
leds [4:0] = 5'b00000;
end end
default: state <= WAIT; default: state <= WAIT;