forked from tanchou/Verilog
Refactor DHT11 module and testbench: update timing parameters, adjust state machine, and correct simulation script paths
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@@ -1,5 +1,8 @@
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@call c:\oss-cad-suite\environment.bat
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@echo off
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mkdir runs
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if "%1"=="sim" call scripts\windows\simulate.bat
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if "%1"=="wave" call scripts\windows\gtkwave.bat
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if "%1"=="clean" call scripts\windows\clean.bat
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