verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Refactor DHT11 module and testbench: update timing parameters, adjust state machine, and correct simulation script paths

Browse Source
This commit is contained in:
Gamenight77
2025-05-21 18:11:28 +02:00
parent cbebf620d5
commit 434381e9b6
5 changed files with 112 additions and 111 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
Semaine_6/DHT11/tests/verilog/tb_dht11.v
View File

@@ -6,13 +6,13 @@ module tb_dht11;
always #18.5 clk = ~clk; // Génère une clock 27 MHz
// === Registres ===
wire io_dht11_sig;
reg dht11_start;
wire dht11_data_ready;
wire dht11_busy;
wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data;
wire dht11_error;
wire io_dht11_sig;
reg dht11_start;
wire dht11_data_ready;
wire dht11_busy;
wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data;
wire dht11_error;
// === Simulation du module DHT11 ===
dht11_model dht11_model (