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Refactor DHT11 module and testbench: update timing parameters, adjust state machine, and correct simulation script paths

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Gamenight77
2025-05-21 18:11:28 +02:00
parent cbebf620d5
commit 434381e9b6
5 changed files with 112 additions and 111 deletions
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3
Semaine_6/DHT11/project.bat
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@@ -1,5 +1,8 @@
@call c:\oss-cad-suite\environment.bat @call c:\oss-cad-suite\environment.bat
@echo off @echo off
mkdir runs
if "%1"=="sim" call scripts\windows\simulate.bat if "%1"=="sim" call scripts\windows\simulate.bat
if "%1"=="wave" call scripts\windows\gtkwave.bat if "%1"=="wave" call scripts\windows\gtkwave.bat
if "%1"=="clean" call scripts\windows\clean.bat if "%1"=="clean" call scripts\windows\clean.bat

2
Semaine_6/DHT11/scripts/windows/gtkwave.bat
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@@ -1,3 +1,3 @@
@echo off @echo off
echo === Lancement de GTKWave === echo === Lancement de GTKWave ===
gtkwave runs/wave.vcd gtkwave runs/sim.vcd

6
Semaine_6/DHT11/src/verilog/dht11_interface.v
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@@ -21,7 +21,7 @@ module dht11_interface #(
localparam T_51US = CLK_FREQ * 51 / 1_000_000; localparam T_51US = CLK_FREQ * 51 / 1_000_000;
localparam T_50US = CLK_FREQ * 50 / 1_000_000; localparam T_50US = CLK_FREQ * 50 / 1_000_000;
localparam T_49US = CLK_FREQ * 49 / 1_000_000; localparam T_49US = CLK_FREQ * 49 / 1_000_000;
localparam T_40US = CLK_FREQ * 40 / 1_000_000; localparam T_41US = CLK_FREQ * 41 / 1_000_000;
localparam T_28US = CLK_FREQ * 28 / 1_000_000; localparam T_28US = CLK_FREQ * 28 / 1_000_000;
localparam T_26US = CLK_FREQ * 26 / 1_000_000; localparam T_26US = CLK_FREQ * 26 / 1_000_000;
localparam T_20US = CLK_FREQ * 20 / 1_000_000; localparam T_20US = CLK_FREQ * 20 / 1_000_000;
@@ -104,13 +104,13 @@ module dht11_interface #(
WAIT_RESPONSE: begin WAIT_RESPONSE: begin
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 0) begin if (sig_in == 0) begin
if (timer > T_20US && timer < T_40US) begin if (timer > T_20US && timer < T_41US) begin
timer <= 0; timer <= 0;
state <= RESPONSE_LOW; state <= RESPONSE_LOW;
end else begin end else begin
state <= ERROR; state <= ERROR;
end end
end else if (timer > T_40US) begin end else if (timer > T_41US) begin
state <= ERROR; state <= ERROR;
end end
end end

198
Semaine_6/DHT11/src/verilog/dht11_model.v
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@@ -1,142 +1,140 @@
module dht11_model ( module dht11_model (
inout wire data, // Ligne de données bidirectionnelle inout wire data, // Ligne de données bidirectionnelle
input wire clk, // Horloge système (50 MHz) input wire clk, // Horloge système (27 MHz)
input wire rst_n // Reset actif bas input wire rst_n // Reset actif bas
); );
// Paramètres pour les timings (basés sur une horloge de 50 MHz, période 20 ns) // Paramètres pour les timings (basés sur une horloge de 27 MHz, période ~37 ns)
localparam CLK_FREQ = 50_000_000; // 50 MHz localparam CLK_FREQ = 27_000_000; // 27 MHz
localparam START_LOW_TIME = 18_000 / 20; // 18 ms pour le signal de démarrage localparam CLK_PERIOD_NS = 37; // 37 ns
localparam START_HIGH_TIME = 40_000 / 20; // 20-40 µs pour le relâchement localparam T_START_LOW = (18_000_000 / CLK_PERIOD_NS); // 18 ms
localparam RESPONSE_LOW = 80_000 / 20; // 80 µs pour la réponse basse localparam T_START_HIGH = (39_500 / CLK_PERIOD_NS); // 40 µs
localparam RESPONSE_HIGH = 80_000 / 20; // 80 µs pour la réponse haute localparam T_RESP_LOW = (80_000 / CLK_PERIOD_NS); // 80 µs
localparam BIT0_LOW = 50_000 / 20; // 50 µs pour bit '0' localparam T_RESP_HIGH = (80_000 / CLK_PERIOD_NS); // 80 µs
localparam BIT1_LOW = 70_000 / 20; // 70 µs pour bit '1' localparam T_BIT0_LOW = (50_000 / CLK_PERIOD_NS); // 50 µs pour bit '0'
localparam DATA_BITS = 40; // 40 bits de données localparam T_BIT1_LOW = (70_000 / CLK_PERIOD_NS); // 70 µs pour bit '1'
localparam T_BIT_GAP = (50_000 / CLK_PERIOD_NS); // 50 µs entre bits
localparam DATA_BITS = 40; // 40 bits de données
// États de la machine à états // États de la machine à états de Moore
localparam IDLE = 3'd0, localparam IDLE = 4'd0,
START = 3'd1, WAIT_START_LOW = 4'd1,
RESPONSE = 3'd2, WAIT_START_HIGH= 4'd2,
SEND_DATA = 3'd3, RESPONSE_LOW = 4'd3,
ENDED = 3'd4; RESPONSE_HIGH = 4'd4,
SEND_BIT_LOW = 4'd5,
SEND_BIT_HIGH = 4'd6,
END_TRANS = 4'd7;
reg [2:0] state, next_state; // Signaux internes
reg [15:0] counter; // Compteur pour les timings reg [3:0] state; // État actuel
reg [5:0] bit_index; // Index du bit à envoyer reg [19:0] counter; // Compteur pour les timings (supporte jusqu'à 20 ms)
reg data_out; // Valeur de sortie sur la ligne data reg [5:0] bit_index; // Index du bit à envoyer
reg data_oe; // Contrôle de l'output enable (1 = sortie, 0 = haute impédance) reg data_out; // Valeur de sortie sur la ligne data
wire data_in; // Valeur lue sur la ligne data reg data_oe; // Output enable (1 = sortie, 0 = haute impédance)
wire data_in; // Valeur lue sur la ligne data
// Données simulées (exemple : humidité = 45.0%, température = 23.0°C) // Données simulées (exemple : humidité = 45.0%, température = 23.0°C)
reg [7:0] humidity_int = 8'h2D; // 45 en décimal reg [7:0] humidity_int = 8'h2D; // 45 en décimal
reg [7:0] humidity_dec = 8'h00; // 0 reg [7:0] humidity_dec = 8'h00; // 0
reg [7:0] temp_int = 8'h17; // 23 en décimal reg [7:0] temp_int = 8'h17; // 23 en décimal
reg [7:0] temp_dec = 8'h00; // 0 reg [7:0] temp_dec = 8'h00; // 0
reg [7:0] checksum; // Checksum = sum des 4 octets reg [7:0] checksum; // Checksum
reg [39:0] data_shift; // Registre pour les 40 bits de données
reg [39:0] data_shift; // Registre pour les 40 bits de données
// Gestion de la ligne bidirectionnelle // Gestion de la ligne bidirectionnelle
assign data = data_oe ? data_out : 1'bz; assign data = data_oe ? data_out : 1'bz;
assign data_in = data; assign data_in = data;
// Calcul du checksum // Calcul du checksum et préparation des données
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
checksum <= 8'h00; checksum <= 8'h00;
end else begin
checksum <= humidity_int + humidity_dec + temp_int + temp_dec;
end
end
// Concaténation des données à envoyer
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
data_shift <= 40'b0; data_shift <= 40'b0;
end else begin end else begin
checksum <= humidity_int + humidity_dec + temp_int + temp_dec;
data_shift <= {humidity_int, humidity_dec, temp_int, temp_dec, checksum}; data_shift <= {humidity_int, humidity_dec, temp_int, temp_dec, checksum};
end end
end end
// Machine à états // Logique séquentielle (machine à états de Moore)
always @(posedge clk or negedge rst_n) begin always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
state <= IDLE; state <= IDLE;
counter <= 16'b0; counter <= 20'b0;
bit_index <= 6'b0; bit_index <= 6'b0;
data_out <= 1'b1; data_out <= 1'b1;
data_oe <= 1'b0; data_oe <= 1'b0;
end else begin end else begin
state <= next_state; counter <= counter + 1; // Incrément du compteur par défaut
case (state) case (state)
IDLE: begin IDLE: begin
counter <= 16'b0; counter <= 20'b0;
bit_index <= 6'b0; bit_index <= 6'b0;
data_out <= 1'b1; data_out <= 1'b1;
data_oe <= 1'b0; data_oe <= 1'b0;
if (data_in === 1'b0) // Vérification explicite pour éviter X
state <= WAIT_START_LOW;
end end
START: begin WAIT_START_LOW: begin
counter <= counter + 1; data_out <= 1'b1;
data_out <= 1'b0; data_oe <= 1'b0;
data_oe <= 1'b1; if (data_in === 1'b1 && counter >= T_START_LOW)
end state <= WAIT_START_HIGH;
RESPONSE: begin else if (data_in === 1'b1)
counter <= counter + 1; state <= IDLE; // Signal de démarrage trop court
if (counter < RESPONSE_LOW) begin end
data_out <= 1'b0; WAIT_START_HIGH: begin
data_oe <= 1'b1; data_out <= 1'b1;
end else begin data_oe <= 1'b0;
data_out <= 1'b1; if (counter >= T_START_HIGH)
data_oe <= 1'b1; state <= RESPONSE_LOW;
end end
end RESPONSE_LOW: begin
SEND_DATA: begin data_out <= 1'b0;
counter <= counter + 1; data_oe <= 1'b1;
if (counter == 0) begin if (counter >= T_RESP_LOW)
data_out <= 1'b0; // Début du bit (toujours bas) state <= RESPONSE_HIGH;
data_oe <= 1'b1; end
end else if (counter == (data_shift[39-bit_index] ? BIT1_LOW : BIT0_LOW)) begin RESPONSE_HIGH: begin
data_out <= 1'b1; // Fin du bit data_out <= 1'b1;
data_oe <= 1'b1; data_oe <= 1'b1;
end else if (counter >= (data_shift[39-bit_index] ? BIT1_LOW + 50 : BIT0_LOW + 50)) begin if (counter >= T_RESP_HIGH)
counter <= 16'b0; state <= SEND_BIT_LOW;
bit_index <= bit_index + 1; end
end SEND_BIT_LOW: begin
end data_out <= 1'b0;
ENDED: begin data_oe <= 1'b1;
if (counter >= (data_shift[39-bit_index] ? T_BIT1_LOW : T_BIT0_LOW))
state <= SEND_BIT_HIGH;
end
SEND_BIT_HIGH: begin
data_out <= 1'b1;
data_oe <= 1'b1;
if (counter >= T_BIT_GAP) begin
counter <= 20'b0;
bit_index <= bit_index + 1;
if (bit_index + 1 < DATA_BITS)
state <= SEND_BIT_LOW;
else
state <= END_TRANS;
end
end
END_TRANS: begin
data_out <= 1'b1;
data_oe <= 1'b0;
counter <= 20'b0;
state <= IDLE;
end
default: begin
state <= IDLE;
counter <= 20'b0;
data_out <= 1'b1; data_out <= 1'b1;
data_oe <= 1'b0; data_oe <= 1'b0;
counter <= 16'b0;
end end
endcase endcase
end end
end end
// Logique de transition des états
always @(*) begin
next_state = state;
case (state)
IDLE: begin
if (data_in == 1'b0) // Détection du signal de démarrage
next_state = START;
end
START: begin
if (counter >= START_LOW_TIME && data_in == 1'b1)
next_state = RESPONSE;
end
RESPONSE: begin
if (counter >= RESPONSE_LOW + RESPONSE_HIGH)
next_state = SEND_DATA;
end
SEND_DATA: begin
if (bit_index >= DATA_BITS)
next_state = ENDED;
end
ENDED: begin
next_state = IDLE;
end
endcase
end
endmodule endmodule

14
Semaine_6/DHT11/tests/verilog/tb_dht11.v
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@@ -6,13 +6,13 @@ module tb_dht11;
always #18.5 clk = ~clk; // Génère une clock 27 MHz always #18.5 clk = ~clk; // Génère une clock 27 MHz
// === Registres === // === Registres ===
wire io_dht11_sig; wire io_dht11_sig;
reg dht11_start; reg dht11_start;
wire dht11_data_ready; wire dht11_data_ready;
wire dht11_busy; wire dht11_busy;
wire [7:0] dht11_temp_data; wire [7:0] dht11_temp_data;
wire [7:0] dht11_hum_data; wire [7:0] dht11_hum_data;
wire dht11_error; wire dht11_error;
// === Simulation du module DHT11 === // === Simulation du module DHT11 ===
dht11_model dht11_model ( dht11_model dht11_model (