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Fix timer conditions in DHT11 state machine for signal detection

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Gamenight77
2025-05-27 13:45:58 +02:00
parent d69a0a4753
commit 4e16bb3cbe
1 changed files with 3 additions and 3 deletions
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6
Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
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@@ -107,7 +107,7 @@ module dht11_interface #(
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 0 && timer > 2) begin if (sig_in == 0) begin
state <= RESPONSE_LOW; state <= RESPONSE_LOW;
timer <= 0; timer <= 0;
@@ -119,7 +119,7 @@ module dht11_interface #(
o_state <= state; o_state <= state;
timer <= timer + 1; timer <= timer + 1;
if (sig_in == 1 && timer > 2) begin if (sig_in == 1 ) begin
timer <= 0; timer <= 0;
state <= RESPONSE_HIGH; state <= RESPONSE_HIGH;
@@ -159,7 +159,7 @@ module dht11_interface #(
bit_index <= bit_index + 1; bit_index <= bit_index + 1;
if (bit_index == 39) begin if (bit_index == 40) begin
state <= DONE; state <= DONE;
end else begin end else begin
state <= READ_BITS_LOW; state <= READ_BITS_LOW;