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This commit is contained in:
Gamenight77
2025-04-28 09:22:17 +02:00
parent a976fcb266
commit 505f71974e
26 changed files with 94421 additions and 4 deletions
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3
Semaine_2/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_fpga.v
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@@ -36,7 +36,7 @@ module ultrasonic_fpga #(
reg [31:0] wait_counter;
always @(posedge clk) begin
always @(posedge clk) begin
sig_int <= sig;
sig_ok <= sig_int;
end
@@ -120,6 +120,7 @@ module ultrasonic_fpga #(
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= TRIG_HIGH;
trig_counter <= 0;
end
end

6
Semaine_2/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_sensor.v
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@@ -7,8 +7,8 @@ module ultrasonic_sensor( // Simulation of an ultrasonic sensor
reg [2:0] state = 3'd0; // State of the FSM
reg [2:0] next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter; // Counter for the trigger pulse
reg [31:0] echo_counter; // Echo signal
reg [15:0] trig_counter = 0; // Counter for the trigger pulse
reg [31:0] echo_counter = 0; // Echo signal
reg valid_trig = 0; // Valid trigger signal
reg echo_sended = 0; // Flag to indicate if echo has been sent
@@ -67,7 +67,7 @@ module ultrasonic_sensor( // Simulation of an ultrasonic sensor
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES-20000 && trig_counter <= TRIG_PULSE_CYCLES+20000) begin
if (trig_counter >= TRIG_PULSE_CYCLES) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;