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Gamenight77
2025-04-28 09:22:17 +02:00
parent a976fcb266
commit 505f71974e
26 changed files with 94421 additions and 4 deletions
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471
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/sim.out Normal file
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#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
S_00000235513c4b70 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
.timescale -9 -12;
P_00000235513be7d0 .param/l "CLK_FREQ" 0 2 13, +C4<00000001100110111111110011000000>;
v0000023551441c40_0 .var "clk", 0 0;
v0000023551441d80_0 .net "distance", 15 0, v00000235513c6040_0; 1 drivers
RS_00000235513ef028 .resolv tri, L_0000023551441380, L_0000023551442d20;
v0000023551441ce0_0 .net8 "sig", 0 0, RS_00000235513ef028; 2 drivers
v00000235514417e0_0 .var "start", 0 0;
S_00000235513c4f10 .scope module, "sensor" "ultrasonic_sensor" 2 22, 3 1 0, S_00000235513c4b70;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INOUT 1 "signal";
P_00000235513c2970 .param/l "CLK_FREQ" 0 3 5, +C4<00000001100110111111110011000000>;
P_00000235513c29a8 .param/l "S_MEASURE_TRIG" 1 3 20, C4<001>;
P_00000235513c29e0 .param/l "S_SEND_ECHO" 1 3 21, C4<010>;
P_00000235513c2a18 .param/l "S_WAIT_TRIG" 1 3 19, C4<000>;
P_00000235513c2a50 .param/l "TRIG_PULSE_CYCLES" 1 3 23, +C4<00000000000000000000000100001110>;
o00000235513eef08 .functor BUFZ 1, c4<z>; HiZ drive
; Elide local net with no drivers, v00000235513c6680_0 name=_ivl_0
v00000235513c5d20_0 .net "clk", 0 0, v0000023551441c40_0; 1 drivers
v00000235513c5c80_0 .var "echo_delay_counter", 15 0;
v00000235513c6400_0 .var "echo_sended", 0 0;
v00000235513c6720_0 .var "next_state", 2 0;
v00000235513c5f00_0 .var "sig_dir", 0 0;
v00000235513c69a0_0 .net8 "signal", 0 0, RS_00000235513ef028; alias, 2 drivers
v00000235513c65e0_0 .var "signal_out", 0 0;
v00000235513c60e0_0 .var "state", 2 0;
v00000235513c6a40_0 .var "trig_counter", 15 0;
v00000235513c67c0_0 .var "valid_trig", 0 0;
E_00000235513bfb50 .event posedge, v00000235513c5d20_0;
E_00000235513bf790 .event anyedge, v00000235513c60e0_0, v00000235513c69a0_0, v00000235513c67c0_0, v00000235513c6400_0;
L_0000023551442d20 .functor MUXZ 1, o00000235513eef08, v00000235513c65e0_0, v00000235513c5f00_0, C4<>;
S_00000235512ada20 .scope module, "uut" "ultrasonic_fpga" 2 15, 4 1 0, S_00000235513c4b70;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "start";
.port_info 2 /INOUT 1 "sig";
.port_info 3 /OUTPUT 16 "distance";
.port_info 4 /OUTPUT 3 "state";
P_00000235512adbb0 .param/l "CLK_FREQ" 0 4 2, +C4<00000001100110111111110011000000>;
P_00000235512adbe8 .param/l "DIST_DIVISOR" 1 4 31, +C4<00000000000000000000011000011110>;
P_00000235512adc20 .param/l "DONE" 1 4 27, C4<101>;
P_00000235512adc58 .param/l "IDLE" 1 4 22, C4<000>;
P_00000235512adc90 .param/l "MAX_CM" 1 4 32, +C4<00000000000000000000000101011110>;
P_00000235512adcc8 .param/l "MEASURE_ECHO" 1 4 26, C4<100>;
P_00000235512add00 .param/l "TIMEOUT_CYCLES" 1 4 33, +C4<11111111111111111111100110001001>;
P_00000235512add38 .param/l "TRIG_HIGH" 1 4 23, C4<001>;
P_00000235512add70 .param/l "TRIG_LOW" 1 4 24, C4<010>;
P_00000235512adda8 .param/l "TRIG_PULSE_CYCLES" 1 4 30, +C4<00000000000000000000000100001110>;
P_00000235512adde0 .param/l "WAIT_ECHO" 1 4 25, C4<011>;
P_00000235512ade18 .param/l "WAIT_NEXT" 1 4 28, C4<110>;
P_00000235512ade50 .param/l "WAIT_NEXT_CYCLES" 1 4 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>;
o00000235513ef178 .functor BUFZ 1, c4<z>; HiZ drive
; Elide local net with no drivers, v00000235513c6360_0 name=_ivl_0
v00000235513c5e60_0 .net "clk", 0 0, v0000023551441c40_0; alias, 1 drivers
v00000235513c6040_0 .var "distance", 15 0;
v00000235513c5fa0_0 .var "distance_counter", 15 0;
v00000235513c6860_0 .var "echo_counter", 31 0;
v00000235513c64a0_0 .var "echo_div_counter", 31 0;
v00000235513c6540_0 .net8 "sig", 0 0, RS_00000235513ef028; alias, 2 drivers
v00000235513c6900_0 .var "sig_dir", 0 0;
v00000235513c5b40_0 .var "sig_int", 0 0;
v00000235513c5be0_0 .var "sig_ok", 0 0;
v00000235513c5dc0_0 .var "sig_out", 0 0;
v00000235513c6180_0 .net "start", 0 0, v00000235514417e0_0; 1 drivers
v00000235513c6220_0 .var "state", 2 0;
v00000235513c62c0_0 .var "trig_counter", 15 0;
v00000235514414c0_0 .var "wait_counter", 31 0;
L_0000023551441380 .functor MUXZ 1, o00000235513ef178, v00000235513c5dc0_0, v00000235513c6900_0, C4<>;
.scope S_00000235512ada20;
T_0 ;
%wait E_00000235513bfb50;
%load/vec4 v00000235513c6540_0;
%assign/vec4 v00000235513c5b40_0, 0;
%load/vec4 v00000235513c5b40_0;
%assign/vec4 v00000235513c5be0_0, 0;
%jmp T_0;
.thread T_0;
.scope S_00000235512ada20;
T_1 ;
%wait E_00000235513bfb50;
%load/vec4 v00000235513c6220_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_1.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_1.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_1.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_1.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_1.4, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_1.5, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_1.6, 6;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%jmp T_1.8;
T_1.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000235513c5dc0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c6900_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c6040_0, 0;
%load/vec4 v00000235513c6180_0;
%flag_set/vec4 8;
%jmp/0xz T_1.9, 8;
%pushi/vec4 1, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c62c0_0, 0;
T_1.9 ;
%jmp T_1.8;
T_1.1 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c5dc0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c6900_0, 0;
%load/vec4 v00000235513c62c0_0;
%pad/u 32;
%cmpi/u 270, 0, 32;
%jmp/0xz T_1.11, 5;
%load/vec4 v00000235513c62c0_0;
%addi 1, 0, 16;
%assign/vec4 v00000235513c62c0_0, 0;
%jmp T_1.12;
T_1.11 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c62c0_0, 0;
%pushi/vec4 2, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
T_1.12 ;
%jmp T_1.8;
T_1.2 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000235513c5dc0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000235513c6900_0, 0;
%pushi/vec4 3, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%jmp T_1.8;
T_1.3 ;
%load/vec4 v00000235513c5be0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.13, 8;
%pushi/vec4 0, 0, 32;
%assign/vec4 v00000235513c6860_0, 0;
%pushi/vec4 4, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%jmp T_1.14;
T_1.13 ;
%load/vec4 v00000235513c6860_0;
%cmpi/u 4294965641, 0, 32;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.15, 5;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c6040_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%jmp T_1.16;
T_1.15 ;
%load/vec4 v00000235513c6860_0;
%addi 1, 0, 32;
%assign/vec4 v00000235513c6860_0, 0;
T_1.16 ;
T_1.14 ;
%jmp T_1.8;
T_1.4 ;
%load/vec4 v00000235513c5be0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.17, 8;
%load/vec4 v00000235513c6860_0;
%cmpi/u 4294965641, 0, 32;
%jmp/0xz T_1.19, 5;
%load/vec4 v00000235513c6860_0;
%addi 1, 0, 32;
%assign/vec4 v00000235513c6860_0, 0;
%jmp T_1.20;
T_1.19 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c6040_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
T_1.20 ;
%jmp T_1.18;
T_1.17 ;
%load/vec4 v00000235513c6860_0;
%addi 1, 0, 32;
%assign/vec4 v00000235513c6860_0, 0;
%load/vec4 v00000235513c64a0_0;
%cmpi/u 1565, 0, 32;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.21, 5;
%pushi/vec4 0, 0, 32;
%assign/vec4 v00000235513c64a0_0, 0;
%load/vec4 v00000235513c5fa0_0;
%addi 1, 0, 16;
%assign/vec4 v00000235513c5fa0_0, 0;
%jmp T_1.22;
T_1.21 ;
%load/vec4 v00000235513c64a0_0;
%addi 1, 0, 32;
%assign/vec4 v00000235513c64a0_0, 0;
T_1.22 ;
%load/vec4 v00000235513c5fa0_0;
%assign/vec4 v00000235513c6040_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
T_1.18 ;
%jmp T_1.8;
T_1.5 ;
%load/vec4 v00000235513c6180_0;
%flag_set/vec4 8;
%jmp/0xz T_1.23, 8;
%pushi/vec4 0, 0, 32;
%assign/vec4 v00000235514414c0_0, 0;
%pushi/vec4 6, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
%jmp T_1.24;
T_1.23 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
T_1.24 ;
%jmp T_1.8;
T_1.6 ;
%load/vec4 v00000235514414c0_0;
%addi 1, 0, 32;
%assign/vec4 v00000235514414c0_0, 0;
%load/vec4 v00000235514414c0_0;
%pad/u 64;
%cmpi/u 2700000, 0, 64;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.25, 5;
%pushi/vec4 1, 0, 3;
%assign/vec4 v00000235513c6220_0, 0;
T_1.25 ;
%jmp T_1.8;
T_1.8 ;
%pop/vec4 1;
%jmp T_1;
.thread T_1;
.scope S_00000235513c4f10;
T_2 ;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000235513c60e0_0, 0, 3;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c67c0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c6400_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c65e0_0, 0, 1;
%end;
.thread T_2;
.scope S_00000235513c4f10;
T_3 ;
%wait E_00000235513bf790;
%load/vec4 v00000235513c60e0_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_3.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_3.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_3.2, 6;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c5f00_0, 0, 1;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
%jmp T_3.4;
T_3.0 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c5f00_0, 0, 1;
%load/vec4 v00000235513c69a0_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_3.5, 4;
%pushi/vec4 1, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
%jmp T_3.6;
T_3.5 ;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
T_3.6 ;
%jmp T_3.4;
T_3.1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c5f00_0, 0, 1;
%load/vec4 v00000235513c67c0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.7, 8;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
T_3.7 ;
%jmp T_3.4;
T_3.2 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000235513c5f00_0, 0, 1;
%load/vec4 v00000235513c6400_0;
%flag_set/vec4 8;
%jmp/0xz T_3.9, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235513c6400_0, 0, 1;
%pushi/vec4 0, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
%jmp T_3.10;
T_3.9 ;
%pushi/vec4 2, 0, 3;
%store/vec4 v00000235513c6720_0, 0, 3;
T_3.10 ;
%jmp T_3.4;
T_3.4 ;
%pop/vec4 1;
%jmp T_3;
.thread T_3, $push;
.scope S_00000235513c4f10;
T_4 ;
%wait E_00000235513bfb50;
%load/vec4 v00000235513c6720_0;
%assign/vec4 v00000235513c60e0_0, 0;
%jmp T_4;
.thread T_4;
.scope S_00000235513c4f10;
T_5 ;
%wait E_00000235513bfb50;
%load/vec4 v00000235513c60e0_0;
%cmpi/e 1, 0, 3;
%jmp/0xz T_5.0, 4;
%load/vec4 v00000235513c69a0_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_5.2, 4;
%load/vec4 v00000235513c6a40_0;
%addi 1, 0, 16;
%assign/vec4 v00000235513c6a40_0, 0;
%jmp T_5.3;
T_5.2 ;
%load/vec4 v00000235513c6a40_0;
%pad/u 32;
%cmpi/u 4294947566, 0, 32;
%flag_inv 5; GE is !LT
%flag_get/vec4 5;
%jmp/0 T_5.6, 5;
%load/vec4 v00000235513c6a40_0;
%pad/u 32;
%cmpi/u 20270, 0, 32;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
T_5.6;
%flag_set/vec4 8;
%jmp/0xz T_5.4, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c67c0_0, 0;
%jmp T_5.5;
T_5.4 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000235513c67c0_0, 0;
T_5.5 ;
T_5.3 ;
T_5.0 ;
%jmp T_5;
.thread T_5;
.scope S_00000235513c4f10;
T_6 ;
%wait E_00000235513bfb50;
%load/vec4 v00000235513c60e0_0;
%cmpi/e 2, 0, 3;
%jmp/0xz T_6.0, 4;
%load/vec4 v00000235513c5c80_0;
%pad/u 32;
%cmpi/e 5800, 0, 32;
%jmp/0xz T_6.2, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v00000235513c65e0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c6400_0, 0;
%jmp T_6.3;
T_6.2 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v00000235513c65e0_0, 0;
%load/vec4 v00000235513c5c80_0;
%addi 1, 0, 16;
%assign/vec4 v00000235513c5c80_0, 0;
T_6.3 ;
%jmp T_6.1;
T_6.0 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v00000235513c5c80_0, 0;
T_6.1 ;
%jmp T_6;
.thread T_6;
.scope S_00000235513c4b70;
T_7 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000023551441c40_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235514417e0_0, 0, 1;
%end;
.thread T_7;
.scope S_00000235513c4b70;
T_8 ;
%delay 18000, 0;
%load/vec4 v0000023551441c40_0;
%inv;
%store/vec4 v0000023551441c40_0, 0, 1;
%jmp T_8;
.thread T_8;
.scope S_00000235513c4b70;
T_9 ;
%vpi_call 2 28 "$dumpfile", "ultrasonic.vcd" {0 0 0};
%vpi_call 2 29 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000235513c4b70 {0 0 0};
%delay 100000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v00000235514417e0_0, 0, 1;
%delay 40000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v00000235514417e0_0, 0, 1;
%delay 600000000, 0;
%vpi_call 2 40 "$display", "Distance mesur\303\251e: %d cm", v0000023551441d80_0 {0 0 0};
%load/vec4 v0000023551441d80_0;
%pad/u 32;
%cmpi/u 0, 0, 32;
%flag_or 5, 4; GT is !LE
%flag_inv 5;
%jmp/0xz T_9.0, 5;
%vpi_call 2 45 "$display", "Distance measured: %d cm", v0000023551441d80_0 {0 0 0};
%jmp T_9.1;
T_9.0 ;
%vpi_call 2 47 "$display", "No distance measured." {0 0 0};
T_9.1 ;
%vpi_call 2 50 "$finish" {0 0 0};
%end;
.thread T_9;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"tb_ultrasonic_fpga.v";
"ultrasonic_sensor.v";
"ultrasonic_fpga.v";

53
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/tb_ultrasonic_fpga.v Normal file
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@@ -0,0 +1,53 @@
`timescale 1ns/1ps
module tb_ultrasonic_fpga;
reg clk = 0;
reg start = 0;
wire sig;
wire [15:0] distance;
// Clock 27MHz => periode = 37ns
always #18 clk = ~clk;
parameter CLK_FREQ = 27_000_000; // 27 MHz
ultrasonic_fpga uut (
.clk(clk),
.start(start),
.sig(sig),
.distance(distance)
);
ultrasonic_sensor sensor (
.clk(clk),
.signal(sig)
);
initial begin
$dumpfile("ultrasonic.vcd");
$dumpvars(0, tb_ultrasonic_fpga);
// Start
#100;
start = 1;
#40;
start = 0;
// Attendre que la distance soit mesurée
// wait (distance > 0);
#600000; // petite marge pour stabiliser
$display("Distance mesurée: %d cm", distance);
// Affiche la distance
if (distance > 0) begin
$display("Distance measured: %d cm", distance);
end else begin
$display("No distance measured.");
end
$finish;
end
endmodule

471
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/tb_ultrasonic_fpga.vvp Normal file
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@@ -0,0 +1,471 @@
#!
:ivl_version "13.0 (devel)" "(s20250103-31-g7e238e7ca-dirty)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 12;
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\system.vpi";
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\v2005_math.vpi";
:vpi_module "C:\Users\louis\Desktop\Stage\OSS-CA~1\lib\ivl\va_math.vpi";
S_000001b750674ff0 .scope module, "tb_ultrasonic_fpga" "tb_ultrasonic_fpga" 2 3;
.timescale -9 -12;
P_000001b75066f080 .param/l "CLK_FREQ" 0 2 13, +C4<00000001100110111111110011000000>;
v000001b7506ef330_0 .var "clk", 0 0;
v000001b7506ef970_0 .net "distance", 15 0, v000001b7506ef5b0_0; 1 drivers
RS_000001b75069f0b8 .resolv tri, L_000001b7506efc90, L_000001b7506f1530;
v000001b7506ef470_0 .net8 "sig", 0 0, RS_000001b75069f0b8; 2 drivers
v000001b7506ef650_0 .var "start", 0 0;
S_000001b750675390 .scope module, "sensor" "ultrasonic_sensor" 2 22, 3 1 0, S_000001b750674ff0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INOUT 1 "signal";
P_000001b750672df0 .param/l "CLK_FREQ" 0 3 5, +C4<00000001100110111111110011000000>;
P_000001b750672e28 .param/l "S_MEASURE_TRIG" 1 3 20, C4<001>;
P_000001b750672e60 .param/l "S_SEND_ECHO" 1 3 21, C4<010>;
P_000001b750672e98 .param/l "S_WAIT_TRIG" 1 3 19, C4<000>;
P_000001b750672ed0 .param/l "TRIG_PULSE_CYCLES" 1 3 23, +C4<00000000000000000000000100001110>;
o000001b75069ef98 .functor BUFZ 1, c4<z>; HiZ drive
; Elide local net with no drivers, v000001b75074a970_0 name=_ivl_0
v000001b75074ae10_0 .net "clk", 0 0, v000001b7506ef330_0; 1 drivers
v000001b75074af30_0 .var "echo_delay_counter", 15 0;
v000001b75068feb0_0 .var "echo_sended", 0 0;
v000001b750675520_0 .var "next_state", 2 0;
v000001b7506755c0_0 .var "sig_dir", 0 0;
v000001b7506effb0_0 .net8 "signal", 0 0, RS_000001b75069f0b8; alias, 2 drivers
v000001b7506ef830_0 .var "signal_out", 0 0;
v000001b7506ef510_0 .var "state", 2 0;
v000001b7506ef0b0_0 .var "trig_counter", 15 0;
v000001b7506efdd0_0 .var "valid_trig", 0 0;
E_000001b750670380 .event posedge, v000001b75074ae10_0;
E_000001b75066fac0 .event anyedge, v000001b7506ef510_0, v000001b7506effb0_0, v000001b7506efdd0_0, v000001b75068feb0_0;
L_000001b7506f1530 .functor MUXZ 1, o000001b75069ef98, v000001b7506ef830_0, v000001b7506755c0_0, C4<>;
S_000001b75074d480 .scope module, "uut" "ultrasonic_fpga" 2 15, 4 1 0, S_000001b750674ff0;
.timescale -9 -12;
.port_info 0 /INPUT 1 "clk";
.port_info 1 /INPUT 1 "start";
.port_info 2 /INOUT 1 "sig";
.port_info 3 /OUTPUT 16 "distance";
.port_info 4 /OUTPUT 3 "state";
P_000001b75074d610 .param/l "CLK_FREQ" 0 4 2, +C4<00000001100110111111110011000000>;
P_000001b75074d648 .param/l "DIST_DIVISOR" 1 4 31, +C4<00000000000000000000011000011110>;
P_000001b75074d680 .param/l "DONE" 1 4 27, C4<101>;
P_000001b75074d6b8 .param/l "IDLE" 1 4 22, C4<000>;
P_000001b75074d6f0 .param/l "MAX_CM" 1 4 32, +C4<00000000000000000000000101011110>;
P_000001b75074d728 .param/l "MEASURE_ECHO" 1 4 26, C4<100>;
P_000001b75074d760 .param/l "TIMEOUT_CYCLES" 1 4 33, +C4<11111111111111111111100110001001>;
P_000001b75074d798 .param/l "TRIG_HIGH" 1 4 23, C4<001>;
P_000001b75074d7d0 .param/l "TRIG_LOW" 1 4 24, C4<010>;
P_000001b75074d808 .param/l "TRIG_PULSE_CYCLES" 1 4 30, +C4<00000000000000000000000100001110>;
P_000001b75074d840 .param/l "WAIT_ECHO" 1 4 25, C4<011>;
P_000001b75074d878 .param/l "WAIT_NEXT" 1 4 28, C4<110>;
P_000001b75074d8b0 .param/l "WAIT_NEXT_CYCLES" 1 4 35, +C4<0000000000000000000000000000000000000000001010010011001011100000>;
o000001b75069f208 .functor BUFZ 1, c4<z>; HiZ drive
; Elide local net with no drivers, v000001b7506ef150_0 name=_ivl_0
v000001b7506efa10_0 .net "clk", 0 0, v000001b7506ef330_0; alias, 1 drivers
v000001b7506ef5b0_0 .var "distance", 15 0;
v000001b7506ef6f0_0 .var "distance_counter", 15 0;
v000001b7506eff10_0 .var "echo_counter", 31 0;
v000001b7506efbf0_0 .var "echo_div_counter", 31 0;
v000001b7506ef790_0 .net8 "sig", 0 0, RS_000001b75069f0b8; alias, 2 drivers
v000001b7506ef1f0_0 .var "sig_dir", 0 0;
v000001b7506ef3d0_0 .var "sig_int", 0 0;
v000001b7506efd30_0 .var "sig_ok", 0 0;
v000001b7506ef8d0_0 .var "sig_out", 0 0;
v000001b7506efab0_0 .net "start", 0 0, v000001b7506ef650_0; 1 drivers
v000001b7506ef290_0 .var "state", 2 0;
v000001b7506efe70_0 .var "trig_counter", 15 0;
v000001b7506efb50_0 .var "wait_counter", 31 0;
L_000001b7506efc90 .functor MUXZ 1, o000001b75069f208, v000001b7506ef8d0_0, v000001b7506ef1f0_0, C4<>;
.scope S_000001b75074d480;
T_0 ;
%wait E_000001b750670380;
%load/vec4 v000001b7506ef790_0;
%assign/vec4 v000001b7506ef3d0_0, 0;
%load/vec4 v000001b7506ef3d0_0;
%assign/vec4 v000001b7506efd30_0, 0;
%jmp T_0;
.thread T_0;
.scope S_000001b75074d480;
T_1 ;
%wait E_000001b750670380;
%load/vec4 v000001b7506ef290_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_1.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_1.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_1.2, 6;
%dup/vec4;
%pushi/vec4 3, 0, 3;
%cmp/u;
%jmp/1 T_1.3, 6;
%dup/vec4;
%pushi/vec4 4, 0, 3;
%cmp/u;
%jmp/1 T_1.4, 6;
%dup/vec4;
%pushi/vec4 5, 0, 3;
%cmp/u;
%jmp/1 T_1.5, 6;
%dup/vec4;
%pushi/vec4 6, 0, 3;
%cmp/u;
%jmp/1 T_1.6, 6;
%pushi/vec4 0, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%jmp T_1.8;
T_1.0 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001b7506ef8d0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b7506ef1f0_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b7506ef5b0_0, 0;
%load/vec4 v000001b7506efab0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.9, 8;
%pushi/vec4 1, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b7506efe70_0, 0;
T_1.9 ;
%jmp T_1.8;
T_1.1 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b7506ef8d0_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b7506ef1f0_0, 0;
%load/vec4 v000001b7506efe70_0;
%pad/u 32;
%cmpi/u 270, 0, 32;
%jmp/0xz T_1.11, 5;
%load/vec4 v000001b7506efe70_0;
%addi 1, 0, 16;
%assign/vec4 v000001b7506efe70_0, 0;
%jmp T_1.12;
T_1.11 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b7506efe70_0, 0;
%pushi/vec4 2, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
T_1.12 ;
%jmp T_1.8;
T_1.2 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001b7506ef8d0_0, 0;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001b7506ef1f0_0, 0;
%pushi/vec4 3, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%jmp T_1.8;
T_1.3 ;
%load/vec4 v000001b7506efd30_0;
%flag_set/vec4 8;
%jmp/0xz T_1.13, 8;
%pushi/vec4 0, 0, 32;
%assign/vec4 v000001b7506eff10_0, 0;
%pushi/vec4 4, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%jmp T_1.14;
T_1.13 ;
%load/vec4 v000001b7506eff10_0;
%cmpi/u 4294965641, 0, 32;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.15, 5;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b7506ef5b0_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%jmp T_1.16;
T_1.15 ;
%load/vec4 v000001b7506eff10_0;
%addi 1, 0, 32;
%assign/vec4 v000001b7506eff10_0, 0;
T_1.16 ;
T_1.14 ;
%jmp T_1.8;
T_1.4 ;
%load/vec4 v000001b7506efd30_0;
%flag_set/vec4 8;
%jmp/0xz T_1.17, 8;
%load/vec4 v000001b7506eff10_0;
%cmpi/u 4294965641, 0, 32;
%jmp/0xz T_1.19, 5;
%load/vec4 v000001b7506eff10_0;
%addi 1, 0, 32;
%assign/vec4 v000001b7506eff10_0, 0;
%jmp T_1.20;
T_1.19 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b7506ef5b0_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
T_1.20 ;
%jmp T_1.18;
T_1.17 ;
%load/vec4 v000001b7506eff10_0;
%addi 1, 0, 32;
%assign/vec4 v000001b7506eff10_0, 0;
%load/vec4 v000001b7506efbf0_0;
%cmpi/u 1565, 0, 32;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.21, 5;
%pushi/vec4 0, 0, 32;
%assign/vec4 v000001b7506efbf0_0, 0;
%load/vec4 v000001b7506ef6f0_0;
%addi 1, 0, 16;
%assign/vec4 v000001b7506ef6f0_0, 0;
%jmp T_1.22;
T_1.21 ;
%load/vec4 v000001b7506efbf0_0;
%addi 1, 0, 32;
%assign/vec4 v000001b7506efbf0_0, 0;
T_1.22 ;
%load/vec4 v000001b7506ef6f0_0;
%assign/vec4 v000001b7506ef5b0_0, 0;
%pushi/vec4 5, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
T_1.18 ;
%jmp T_1.8;
T_1.5 ;
%load/vec4 v000001b7506efab0_0;
%flag_set/vec4 8;
%jmp/0xz T_1.23, 8;
%pushi/vec4 0, 0, 32;
%assign/vec4 v000001b7506efb50_0, 0;
%pushi/vec4 6, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
%jmp T_1.24;
T_1.23 ;
%pushi/vec4 0, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
T_1.24 ;
%jmp T_1.8;
T_1.6 ;
%load/vec4 v000001b7506efb50_0;
%addi 1, 0, 32;
%assign/vec4 v000001b7506efb50_0, 0;
%load/vec4 v000001b7506efb50_0;
%pad/u 64;
%cmpi/u 2700000, 0, 64;
%flag_inv 5; GE is !LT
%jmp/0xz T_1.25, 5;
%pushi/vec4 1, 0, 3;
%assign/vec4 v000001b7506ef290_0, 0;
T_1.25 ;
%jmp T_1.8;
T_1.8 ;
%pop/vec4 1;
%jmp T_1;
.thread T_1;
.scope S_000001b750675390;
T_2 ;
%pushi/vec4 0, 0, 3;
%store/vec4 v000001b7506ef510_0, 0, 3;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506efdd0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b75068feb0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506ef830_0, 0, 1;
%end;
.thread T_2;
.scope S_000001b750675390;
T_3 ;
%wait E_000001b75066fac0;
%load/vec4 v000001b7506ef510_0;
%dup/vec4;
%pushi/vec4 0, 0, 3;
%cmp/u;
%jmp/1 T_3.0, 6;
%dup/vec4;
%pushi/vec4 1, 0, 3;
%cmp/u;
%jmp/1 T_3.1, 6;
%dup/vec4;
%pushi/vec4 2, 0, 3;
%cmp/u;
%jmp/1 T_3.2, 6;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506755c0_0, 0, 1;
%pushi/vec4 0, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
%jmp T_3.4;
T_3.0 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506755c0_0, 0, 1;
%load/vec4 v000001b7506effb0_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_3.5, 4;
%pushi/vec4 1, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
%jmp T_3.6;
T_3.5 ;
%pushi/vec4 0, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
T_3.6 ;
%jmp T_3.4;
T_3.1 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506755c0_0, 0, 1;
%load/vec4 v000001b7506efdd0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.7, 8;
%pushi/vec4 2, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
T_3.7 ;
%jmp T_3.4;
T_3.2 ;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b7506755c0_0, 0, 1;
%load/vec4 v000001b75068feb0_0;
%flag_set/vec4 8;
%jmp/0xz T_3.9, 8;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b75068feb0_0, 0, 1;
%pushi/vec4 0, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
%jmp T_3.10;
T_3.9 ;
%pushi/vec4 2, 0, 3;
%store/vec4 v000001b750675520_0, 0, 3;
T_3.10 ;
%jmp T_3.4;
T_3.4 ;
%pop/vec4 1;
%jmp T_3;
.thread T_3, $push;
.scope S_000001b750675390;
T_4 ;
%wait E_000001b750670380;
%load/vec4 v000001b750675520_0;
%assign/vec4 v000001b7506ef510_0, 0;
%jmp T_4;
.thread T_4;
.scope S_000001b750675390;
T_5 ;
%wait E_000001b750670380;
%load/vec4 v000001b7506ef510_0;
%cmpi/e 1, 0, 3;
%jmp/0xz T_5.0, 4;
%load/vec4 v000001b7506effb0_0;
%pad/u 32;
%cmpi/e 1, 0, 32;
%jmp/0xz T_5.2, 4;
%load/vec4 v000001b7506ef0b0_0;
%addi 1, 0, 16;
%assign/vec4 v000001b7506ef0b0_0, 0;
%jmp T_5.3;
T_5.2 ;
%load/vec4 v000001b7506ef0b0_0;
%pad/u 32;
%cmpi/u 4294947566, 0, 32;
%flag_inv 5; GE is !LT
%flag_get/vec4 5;
%jmp/0 T_5.6, 5;
%load/vec4 v000001b7506ef0b0_0;
%pad/u 32;
%cmpi/u 20270, 0, 32;
%flag_get/vec4 4;
%flag_get/vec4 5;
%or;
%and;
T_5.6;
%flag_set/vec4 8;
%jmp/0xz T_5.4, 8;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b7506efdd0_0, 0;
%jmp T_5.5;
T_5.4 ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001b7506efdd0_0, 0;
T_5.5 ;
T_5.3 ;
T_5.0 ;
%jmp T_5;
.thread T_5;
.scope S_000001b750675390;
T_6 ;
%wait E_000001b750670380;
%load/vec4 v000001b7506ef510_0;
%cmpi/e 2, 0, 3;
%jmp/0xz T_6.0, 4;
%load/vec4 v000001b75074af30_0;
%pad/u 32;
%cmpi/e 5800, 0, 32;
%jmp/0xz T_6.2, 4;
%pushi/vec4 0, 0, 1;
%assign/vec4 v000001b7506ef830_0, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b75068feb0_0, 0;
%jmp T_6.3;
T_6.2 ;
%pushi/vec4 1, 0, 1;
%assign/vec4 v000001b7506ef830_0, 0;
%load/vec4 v000001b75074af30_0;
%addi 1, 0, 16;
%assign/vec4 v000001b75074af30_0, 0;
T_6.3 ;
%jmp T_6.1;
T_6.0 ;
%pushi/vec4 0, 0, 16;
%assign/vec4 v000001b75074af30_0, 0;
T_6.1 ;
%jmp T_6;
.thread T_6;
.scope S_000001b750674ff0;
T_7 ;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506ef330_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506ef650_0, 0, 1;
%end;
.thread T_7;
.scope S_000001b750674ff0;
T_8 ;
%delay 18000, 0;
%load/vec4 v000001b7506ef330_0;
%inv;
%store/vec4 v000001b7506ef330_0, 0, 1;
%jmp T_8;
.thread T_8;
.scope S_000001b750674ff0;
T_9 ;
%vpi_call 2 28 "$dumpfile", "ultrasonic.vcd" {0 0 0};
%vpi_call 2 29 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001b750674ff0 {0 0 0};
%delay 100000, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b7506ef650_0, 0, 1;
%delay 40000, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b7506ef650_0, 0, 1;
%delay 600000000, 0;
%vpi_call 2 40 "$display", "Distance mesur\303\251e: %d cm", v000001b7506ef970_0 {0 0 0};
%load/vec4 v000001b7506ef970_0;
%pad/u 32;
%cmpi/u 0, 0, 32;
%flag_or 5, 4; GT is !LE
%flag_inv 5;
%jmp/0xz T_9.0, 5;
%vpi_call 2 45 "$display", "Distance measured: %d cm", v000001b7506ef970_0 {0 0 0};
%jmp T_9.1;
T_9.0 ;
%vpi_call 2 47 "$display", "No distance measured." {0 0 0};
T_9.1 ;
%vpi_call 2 50 "$finish" {0 0 0};
%end;
.thread T_9;
# The file index is used to find the file name in the following table.
:file_names 5;
"N/A";
"<interactive>";
"tb_ultrasonic_fpga.v";
"ultrasonic_sensor.v";
"ultrasonic_fpga.v";

67107
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic.vcd Normal file
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134
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_fpga.v Normal file
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@@ -0,0 +1,134 @@
module ultrasonic_fpga #(
parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
)(
input wire clk,
input wire start,
inout wire sig, // Broche bidirectionnelle vers le capteur
output reg [15:0] distance, // Distance mesurée en cm
output reg [2:0] state
);
reg [15:0] trig_counter;
reg [31:0] echo_counter;
reg [31:0] echo_div_counter;
reg [15:0] distance_counter;
reg sig_out;
reg sig_dir; // 1: output, 0: input
assign sig = sig_dir ? sig_out : 1'bz; // bz pour dire que le fpga laisse le fils libre et n'oblige pas de valeur
reg sig_int, sig_ok;
localparam IDLE = 3'd0,
TRIG_HIGH = 3'd1,
TRIG_LOW = 3'd2,
WAIT_ECHO = 3'd3,
MEASURE_ECHO = 3'd4,
DONE = 3'd5,
WAIT_NEXT = 3'd6;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
localparam integer MAX_CM = 350;
localparam integer TIMEOUT_CYCLES = (MAX_CM * 58 * CLK_FREQ) / 1_000_000;
localparam WAIT_NEXT_CYCLES = (CLK_FREQ / 1000) * 100; // 60 ms
reg [31:0] wait_counter;
always @(posedge clk) begin
sig_int <= sig;
sig_ok <= sig_int;
end
always @(posedge clk) begin // FSM
case (state)
IDLE: begin
sig_out <= 0;
sig_dir <= 1;
distance <= 0;
if (start) begin
state <= TRIG_HIGH;
trig_counter <= 0;
end
end
TRIG_HIGH: begin
sig_out <= 1;
sig_dir <= 1;
if (trig_counter < TRIG_PULSE_CYCLES) begin
trig_counter <= trig_counter + 1;
end else begin
trig_counter <= 0;
state <= TRIG_LOW;
end
end
TRIG_LOW: begin
sig_out <= 0;
sig_dir <= 0; // Mettre en entrée
state <= WAIT_ECHO;
end
WAIT_ECHO: begin
if (sig_ok) begin
echo_counter <= 0;
state <= MEASURE_ECHO;
end else if (echo_counter >= TIMEOUT_CYCLES) begin
distance <= 0;
state <= DONE;
end else begin
echo_counter <= echo_counter + 1;
end
end
MEASURE_ECHO: begin
if (sig_ok) begin
if (echo_counter < TIMEOUT_CYCLES) begin
echo_counter <= echo_counter + 1;
end else begin
distance <= 0;
state <= DONE;
end
end else begin //Comptage par cycle de dist diviseur
echo_counter <= echo_counter + 1;
if (echo_div_counter >= DIST_DIVISOR - 1) begin
echo_div_counter <= 0;
distance_counter <= distance_counter + 1;
end else begin
echo_div_counter <= echo_div_counter + 1;
end
distance <= distance_counter;
state <= DONE;
end
end
DONE: begin
if (start) begin
wait_counter <= 0;
state <= WAIT_NEXT;
end else begin
state <= IDLE;
end
end
WAIT_NEXT: begin
wait_counter <= wait_counter + 1;
if (wait_counter >= WAIT_NEXT_CYCLES) begin
state <= TRIG_HIGH;
trig_counter <= 0;
end
end
default: begin
state <= IDLE; // Reset to IDLE state in case of an error
end
endcase
end
endmodule

95
Semaine_3/Capteur_recule_bidirectionel_V2/Ultrasonic/ultrasonic_sensor.v Normal file
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module ultrasonic_sensor( // Simulation of an ultrasonic sensor
input wire clk,
inout wire signal // Signal from the ultrasonic sensor
);
parameter integer CLK_FREQ = 27_000_000;
reg [2:0] state = 3'd0; // State of the FSM
reg [2:0] next_state;
reg sig_dir; // 1: output, 0: input
reg [15:0] trig_counter = 0; // Counter for the trigger pulse
reg [31:0] echo_counter = 0; // Echo signal
reg valid_trig = 0; // Valid trigger signal
reg echo_sended = 0; // Flag to indicate if echo has been sent
reg signal_out = 0;
assign signal = sig_dir ? signal_out : 1'bz; // Assign the signal to the output if sig_dir is high, otherwise set it to high impedance
localparam S_WAIT_TRIG = 3'd0,
S_MEASURE_TRIG = 3'd1,
S_SEND_ECHO = 3'd2;
localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
always @(*) begin
case (state)
S_WAIT_TRIG: begin
sig_dir = 0;
if (signal == 1) begin
next_state = S_MEASURE_TRIG;
end else begin
next_state = S_WAIT_TRIG;
end
end
S_MEASURE_TRIG: begin
sig_dir = 0;
if (valid_trig)begin
next_state = S_SEND_ECHO;
end
end
S_SEND_ECHO: begin
sig_dir = 1; // Mettre en sortie
if (echo_sended) begin
echo_sended = 0; // Reset flag
next_state = S_WAIT_TRIG;
end else begin
next_state = S_SEND_ECHO;
end
end
default: begin
sig_dir = 0;
next_state = S_WAIT_TRIG;
end
endcase
end
always @(posedge clk) begin
state <= next_state;
end
always @(posedge clk) begin
if (state == S_MEASURE_TRIG) begin
if (signal == 1) begin
trig_counter <= trig_counter + 1;
end else begin
if (trig_counter >= TRIG_PULSE_CYCLES) begin
valid_trig <= 1;
end else begin
valid_trig <= 0;
end
end
end
end
reg [15:0] echo_delay_counter;
always @(posedge clk) begin
if (state == S_SEND_ECHO) begin
if (echo_delay_counter == 5800) begin //
signal_out <= 0;
echo_sended <= 1;
end else begin
signal_out <= 1;
echo_delay_counter <= echo_delay_counter + 1;
end
end else begin
echo_delay_counter <= 0;
end
end
endmodule