verlan/Verilog_Louis
1
0
Fork 0
forked from tanchou/Verilog
Code Pull Requests Activity

Add DHT11 UART communication module and related components

Browse Source 
- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.
This commit is contained in:
Louis TANCHOU
2025-05-22 12:27:16 +02:00
parent a541e033d7
commit 54bf6df85b
22 changed files with 1259 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
Semaine_6/DHT11/src/verilog/dht11_interface.v
View File

@@ -14,7 +14,7 @@ module dht11_interface #(
// === DHT11 INTERFACE ===
// === PARAMÈTRES ===
localparam T_18MS = CLK_FREQ * 18 / 1000; // cycles pour 18ms
localparam T_18MS = CLK_FREQ * 18 / 1_000; // cycles pour 18ms a partir
localparam T_80US = CLK_FREQ * 81 / 1_000_000;
localparam T_79US = CLK_FREQ * 79 / 1_000_000;
localparam T_71US = CLK_FREQ * 71 / 1_000_000;
@@ -73,8 +73,8 @@ module dht11_interface #(
case (state)
IDLE: begin
sig_dir <= 1;
sig_out <= 1;
sig_dir <= 0;
//sig_out <= 1;
timer <= 0;
bit_index <= 0;
raw_data <= 0;
@@ -103,10 +103,12 @@ module dht11_interface #(
WAIT_RESPONSE: begin
timer <= timer + 1;
if (sig_in == 0) begin
if (timer > T_20US && timer < T_41US) begin
timer <= 0;
state <= RESPONSE_LOW;
timer <= 0;
end else begin
state <= ERROR;
end
@@ -154,7 +156,7 @@ module dht11_interface #(
end else begin
state <= ERROR;
end
end else if (timer > T_28US) begin
end else if (timer > T_51US) begin
state <= ERROR;
end
end
@@ -162,7 +164,7 @@ module dht11_interface #(
READ_BITS_HIGH: begin // entre 26 et 28us = 0 et ~70us = 1
timer <= timer + 1;
if (sig_in == 0) begin
if (timer < T_26US) begin
if (timer <= T_26US) begin
state <= ERROR;
end
@@ -188,7 +190,7 @@ module dht11_interface #(
temp_dec <= raw_data[15:8];
checksum <= raw_data[7:0];
if (checksum == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
if (raw_data[7:0] == (raw_data[39:32] + raw_data[31:24] + raw_data[23:16] + raw_data[15:8])) begin
o_hum_data <= raw_data[39:32];
o_temp_data <= raw_data[23:16];
o_dht11_data_ready <= 1;

88
Semaine_6/DHT11/src/verilog/dht11_model.v
View File

@@ -1,22 +1,25 @@
module dht11_model (
module dht11_model #(
parameter CLK_FREQ = 27_000_000
)
(
inout wire data, // Ligne de données bidirectionnelle
input wire clk, // (27 MHz)
input wire clk, // Horloge système (27 MHz)
input wire rst_n // Reset actif bas
);
// Paramètres pour les timings (basés sur une horloge de 27 MHz, période ~37 ns)
localparam CLK_FREQ = 27_000_000; // 27 MHz
localparam CLK_PERIOD_NS = 37; // 37 ns
localparam T_START_LOW = (18_000_000 / CLK_PERIOD_NS); // 18 ms
localparam T_START_HIGH = (39_500 / CLK_PERIOD_NS); // 40 µs
localparam integer CLK_PERIOD_NS = (1_000_000_000 / CLK_FREQ); // 37 ns
localparam T_START_LOW = (17_000_000 / CLK_PERIOD_NS); // 17 ms (ajusté selon votre code)
localparam T_START_HIGH = (40_000 / CLK_PERIOD_NS); // 40 µs
localparam T_RESP_LOW = (80_000 / CLK_PERIOD_NS); // 80 µs
localparam T_RESP_HIGH = (80_000 / CLK_PERIOD_NS); // 80 µs
localparam T_BIT0_LOW = (50_000 / CLK_PERIOD_NS); // 50 µs pour bit '0'
localparam T_BIT1_LOW = (70_000 / CLK_PERIOD_NS); // 70 µs pour bit '1'
localparam T_BIT_LOW = (50_000 / CLK_PERIOD_NS); // 50 µs pour le signal LOW de chaque bit
localparam T_BIT0_HIGH = (27_000 / CLK_PERIOD_NS); // 26 µs pour le signal HIGH d'un bit '0'
localparam T_BIT1_HIGH = (70_000 / CLK_PERIOD_NS); // 70 µs pour le signal HIGH d'un bit '1'
localparam T_BIT_GAP = (50_000 / CLK_PERIOD_NS); // 50 µs entre bits
localparam DATA_BITS = 40; // 40 bits de données
// États de la machine à états de Moore
// États de la machine à états de Moore
localparam IDLE = 4'd0,
WAIT_START_LOW = 4'd1,
WAIT_START_HIGH= 4'd2,
@@ -24,11 +27,12 @@ module dht11_model (
RESPONSE_HIGH = 4'd4,
SEND_BIT_LOW = 4'd5,
SEND_BIT_HIGH = 4'd6,
END_TRANS = 4'd7;
END_TRANS = 4'd7,
LAST_BIT_LOW = 4'd8;
// Signaux internes
reg [3:0] state; // État actuel
reg [19:0] counter; // Compteur pour les timings (supporte jusqu'à 20 ms)
reg [31:0] counter; // Compteur pour les timings (supporte jusqu'à 20 ms)
reg [5:0] bit_index; // Index du bit à envoyer
reg data_out; // Valeur de sortie sur la ligne data
reg data_oe; // Output enable (1 = sortie, 0 = haute impédance)
@@ -61,75 +65,105 @@ module dht11_model (
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
state <= IDLE;
counter <= 20'b0;
counter <= 32'b0;
bit_index <= 6'b0;
data_out <= 1'b1;
data_oe <= 1'b0;
end else begin
counter <= counter + 1; // Incrément du compteur par défaut
// assert (bit_index < DATA_BITS) else $error("Index out of bounds: %d", bit_index);
case (state)
IDLE: begin
counter <= 20'b0;
counter <= 32'b0;
bit_index <= 6'b0;
data_out <= 1'b1;
data_oe <= 1'b0;
if (data_in === 1'b0) // Vérification explicite pour éviter X
if (data_in === 1'b0) begin
state <= WAIT_START_LOW;
end
end
WAIT_START_LOW: begin
data_out <= 1'b1;
data_oe <= 1'b0;
if (data_in === 1'b1 && counter >= T_START_LOW)
if (data_in === 1'b1 && counter >= T_START_LOW) begin
state <= WAIT_START_HIGH;
else if (data_in === 1'b1)
counter <= 32'b0;
$display("17ms");
end else if (data_in === 1'b1) begin
state <= IDLE; // Signal de démarrage trop court
end
end
WAIT_START_HIGH: begin
data_out <= 1'b1;
data_oe <= 1'b0;
if (counter >= T_START_HIGH)
if (counter >= T_START_HIGH) begin
state <= RESPONSE_LOW;
counter <= 32'b0;
end
end
RESPONSE_LOW: begin
data_out <= 1'b0;
data_oe <= 1'b1;
if (counter >= T_RESP_LOW)
if (counter >= T_RESP_LOW) begin
state <= RESPONSE_HIGH;
counter <= 32'b0;
end
end
RESPONSE_HIGH: begin
data_out <= 1'b1;
data_oe <= 1'b1;
if (counter >= T_RESP_HIGH)
if (counter >= T_RESP_HIGH) begin
counter <= 32'b0;
state <= SEND_BIT_LOW;
end
end
SEND_BIT_LOW: begin
data_out <= 1'b0;
data_oe <= 1'b1;
if (counter >= (data_shift[39-bit_index] ? T_BIT1_LOW : T_BIT0_LOW))
if (counter >= T_BIT_LOW) begin
state <= SEND_BIT_HIGH;
counter <= 32'b0;
end
end
SEND_BIT_HIGH: begin
data_out <= 1'b1;
data_oe <= 1'b1;
if (counter >= T_BIT_GAP) begin
counter <= 20'b0;
if (counter >= (data_shift[39-bit_index] ? T_BIT1_HIGH : T_BIT0_HIGH)) begin
counter <= 32'b0;
bit_index <= bit_index + 1;
if (bit_index + 1 < DATA_BITS)
if (bit_index + 1 < DATA_BITS) begin
state <= SEND_BIT_LOW;
else
state <= END_TRANS;
end else begin
state <= LAST_BIT_LOW;
bit_index <= 6'b0;
counter <= 32'b0;
end
end
end
LAST_BIT_LOW: begin
data_out <= 1'b0;
data_oe <= 1'b1;
if (counter >= T_BIT_LOW) begin
state <= END_TRANS;
counter <= 32'b0;
end
end
END_TRANS: begin
data_out <= 1'b1;
data_oe <= 1'b0;
counter <= 20'b0;
counter <= 32'b0;
state <= IDLE;
end
default: begin
state <= IDLE;
counter <= 20'b0;
counter <= 32'b0;
data_out <= 1'b1;
data_oe <= 1'b0;
end

2
Semaine_6/DHT11/tests/verilog/tb_dht11.v
View File

@@ -33,6 +33,8 @@ module tb_dht11;
.o_dht11_error(dht11_error)
);
pullup(io_dht11_sig);
// === TEST SEQUENCE ===
initial begin
$dumpfile("runs/sim.vcd");