Add DHT11 UART communication module and related components

- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.

Semaine_6/DHT11/tests/verilog/tb_dht11.v

@@ -33,6 +33,8 @@ module tb_dht11;
         .o_dht11_error(dht11_error)
     );
 
+    pullup(io_dht11_sig);
+
     // === TEST SEQUENCE ===
     initial begin
         $dumpfile("runs/sim.vcd");