Add DHT11 UART communication module and related components

- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.

Semaine_6/DHT11_UART/IP/verilog/fifo.v

@@ -0,0 +1,43 @@
+ module fifo #(
+	parameter       SIZE = 16,
+	parameter       WIDTH = 8
+)(
+    input wire              clk,
+    input wire              wr_en,
+    input wire[WIDTH-1:0]   wr_data,
+    input wire              rd_en,
+    output reg[WIDTH-1:0]   rd_data,
+
+    output wire             full,
+    output wire             empty
+);
+
+    reg [WIDTH-1:0]         fifo[0:SIZE-1];
+    reg [3:0]               wr_ptr;
+    reg [3:0]               rd_ptr;
+    reg [3:0]               count;
+
+    assign full = (count == SIZE);
+    assign empty = (count == 0);
+
+    initial begin
+        wr_ptr = 0;
+        rd_ptr = 0;
+        count = 0;
+    end
+
+    always @(posedge clk) begin // IN
+        if (wr_en && !full) begin
+            fifo[wr_ptr] <= wr_data;
+            wr_ptr <= (wr_ptr + 1) % SIZE;
+            count <= count + 1;
+        end
+
+        if (rd_en && !empty) begin // OUT
+            rd_data <= fifo[rd_ptr];
+            rd_ptr <= (rd_ptr + 1) % SIZE;
+            count <= count - 1;
+        end
+    end
+    
+endmodule