Add DHT11 UART communication module and related components

- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.

Semaine_6/DHT11_UART/project.sh

@@ -0,0 +1,24 @@
+#!/bin/bash
+
+# Charger l'environnement OSS CAD Suite
+source /home/louis/oss-cad-suite/environment
+
+mkdir -p runs
+
+case "$1" in
+  sim)
+    bash scripts/linux/simulate.sh
+    ;;
+  wave)
+    bash scripts/linux/gtkwave.sh
+    ;;
+  clean)
+    bash scripts/linux/clean.sh
+    ;;
+  build)
+    bash scripts/linux/build.sh
+    ;;
+  *)
+    echo "Usage: $0 {sim|wave|clean|build}"
+    ;;
+esac