forked from tanchou/Verilog
Add DHT11 UART communication module and related components
- Implemented a FIFO buffer in Verilog for data storage. - Created a simplified UART transmitter (txuartlite) for serial communication. - Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow. - Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission. - Added a testbench (tb_dht11) for simulating the DHT11 module functionality. - Updated README with project description and command references. - Created build and simulation scripts for both Linux and Windows environments. - Added constraints file for hardware configuration. - Implemented a state machine for managing measurement and data transmission.
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Semaine_6/DHT11_UART/scripts/linux/clean.sh
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Semaine_6/DHT11_UART/scripts/linux/clean.sh
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#!/bin/bash
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echo "=== Nettoyage des fichiers générés ==="
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rm -rf runs/*
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