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forked from tanchou/Verilog

Add DHT11 UART communication module and related components

- Implemented a FIFO buffer in Verilog for data storage.
- Created a simplified UART transmitter (txuartlite) for serial communication.
- Developed a UART transmission FIFO (uart_tx_fifo) to manage data flow.
- Designed the top-level module (dht11_uart_top) to interface with the DHT11 sensor and handle data transmission.
- Added a testbench (tb_dht11) for simulating the DHT11 module functionality.
- Updated README with project description and command references.
- Created build and simulation scripts for both Linux and Windows environments.
- Added constraints file for hardware configuration.
- Implemented a state machine for managing measurement and data transmission.
This commit is contained in:
2025-05-22 12:27:16 +02:00
parent a541e033d7
commit 54bf6df85b
22 changed files with 1259 additions and 34 deletions

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@echo off
echo === Nettoyage du dossier runs ===
rd /s /q runs
mkdir runs