Add initial design files for 27 MHz clock counter

- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.

Introduction/counter/Makefile

@@ -0,0 +1,21 @@
+TOP = top
+DEVICE = GW2AR-18
+
+all: $(TOP).fs
+
+$(TOP).json: $(TOP).v counter.v
+	yosys -p "read_verilog $(TOP).v counter.v; synth_gowin -top $(TOP) -json $(TOP).json"
+
+$(TOP).asc: $(TOP).json tangnano20k.cst
+	nextpnr-gowin --json $(TOP).json --device $(DEVICE) --cst tangnano20k.cst --write $(TOP).asc
+
+$(TOP).fs: $(TOP).asc
+	gowin_pack $(TOP).asc $(TOP).fs
+
+prog: $(TOP).fs
+	openFPGALoader -b tangnano20k $(TOP).fs
+
+clean:
+	rm -f $(TOP).json $(TOP).asc $(TOP).fs
+
+.PHONY: all prog clean

Introduction/counter/counter.v

@@ -1,12 +1,12 @@
 module counter (
     input wire clk,
-    input wire rst,
+    input wire btn1,
     output reg [3:0] count
     );
 
     always @(posedge clk)
     begin
-        if(rst)
+        if(btn1)
             count <= 4'b0000;
         else
             count <= count + 1;

Introduction/counter/counter_compiller.vvp

@@ -0,0 +1,82 @@
+#! 
+:ivl_version "13.0 (devel)" "(s20250103-26-gb0c57ab17-dirty)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\system.vpi";
+:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_sys.vpi";
+:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\vhdl_textio.vpi";
+:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\v2005_math.vpi";
+:vpi_module "C:\Users\louis\BUT2\Verilog\OSS-CA~1\lib\ivl\va_math.vpi";
+S_000001add64e99e0 .scope module, "tb_counter" "tb_counter" 2 1;
+ .timescale 0 0;
+v000001add64e9da0_0 .var "clk", 0 0;
+v000001add64e81c0_0 .net "count", 3 0, v000001add64b6a10_0;  1 drivers
+v000001add64e8260_0 .var "rst", 0 0;
+S_000001add64e9b70 .scope module, "counter_inst" "counter" 2 6, 3 1 0, S_000001add64e99e0;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "clk";
+    .port_info 1 /INPUT 1 "rst";
+    .port_info 2 /OUTPUT 4 "count";
+v000001add64b6e60_0 .net "clk", 0 0, v000001add64e9da0_0;  1 drivers
+v000001add64b6a10_0 .var "count", 3 0;
+v000001add64e9d00_0 .net "rst", 0 0, v000001add64e8260_0;  1 drivers
+E_000001add63cc830 .event posedge, v000001add64b6e60_0;
+    .scope S_000001add64e9b70;
+T_0 ;
+    %wait E_000001add63cc830;
+    %load/vec4 v000001add64e9d00_0;
+    %flag_set/vec4 8;
+    %jmp/0xz  T_0.0, 8;
+    %pushi/vec4 0, 0, 4;
+    %assign/vec4 v000001add64b6a10_0, 0;
+    %jmp T_0.1;
+T_0.0 ;
+    %load/vec4 v000001add64b6a10_0;
+    %addi 1, 0, 4;
+    %assign/vec4 v000001add64b6a10_0, 0;
+T_0.1 ;
+    %jmp T_0;
+    .thread T_0;
+    .scope S_000001add64e99e0;
+T_1 ;
+    %delay 5, 0;
+    %load/vec4 v000001add64e9da0_0;
+    %inv;
+    %store/vec4 v000001add64e9da0_0, 0, 1;
+    %jmp T_1;
+    .thread T_1;
+    .scope S_000001add64e99e0;
+T_2 ;
+    %vpi_call 2 15 "$dumpfile", "dump.vcd" {0 0 0};
+    %vpi_call 2 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001add64e9b70 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v000001add64e9da0_0, 0;
+    %pushi/vec4 0, 0, 1;
+    %assign/vec4 v000001add64e8260_0, 0;
+    %delay 20, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001add64e8260_0, 0, 1;
+    %delay 80, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001add64e8260_0, 0, 1;
+    %delay 50, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001add64e8260_0, 0, 1;
+    %delay 20, 0;
+    %vpi_call 2 26 "$finish" {0 0 0};
+    %end;
+    .thread T_2;
+    .scope S_000001add64e99e0;
+T_3 ;
+    %delay 5, 0;
+    %load/vec4 v000001add64e9da0_0;
+    %inv;
+    %store/vec4 v000001add64e9da0_0, 0, 1;
+    %jmp T_3;
+    .thread T_3;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    ".\tb_counter.v";
+    ".\counter.v";

Introduction/counter/dump.vcd

@@ -1,5 +1,5 @@
 $date
-	Sat Mar 22 10:16:37 2025
+	Mon Apr 14 15:59:40 2025
 $end
 $version
 	Icarus Verilog

Introduction/counter/tangnano20k.cst

@@ -0,0 +1,14 @@
+# Horloge 27 MHz (souvent sur PIN4)
+IO_LOC "clk" 4;
+IO_PORT "clk" IO_TYPE=LVCMOS33;
+
+# Bouton KEY1 (utilisé ici comme btn1 pour reset)
+IO_LOC "btn1" 88;
+IO_PORT "btn1" IO_TYPE=LVCMOS33;
+
+# LEDs (pour afficher le compteur)
+IO_LOC "count[0]" 15;
+IO_LOC "count[1]" 16;
+IO_LOC "count[2]" 17;
+IO_LOC "count[3]" 18;
+IO_PORT "count[3:0]" IO_TYPE=LVCMOS33;

Introduction/counter/top.v

@@ -0,0 +1,13 @@
+module top (
+    input wire clk,
+    input wire btn1,
+    output wire [3:0] count
+);
+
+    counter uut (
+        .clk(clk),
+        .btn1(btn1),
+        .count(count)
+    );
+
+endmodule

README.md

@@ -1,2 +1,6 @@
 # Verilog
 
+## Command
+### Upload on fpga
+yosys -p "synth_ecp5 -json design.json" counter.v
+nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc