Add initial design files for 27 MHz clock counter

- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.

Introduction/counter/Makefile

@@ -0,0 +1,21 @@
+TOP = top
+DEVICE = GW2AR-18
+
+all: $(TOP).fs
+
+$(TOP).json: $(TOP).v counter.v
+	yosys -p "read_verilog $(TOP).v counter.v; synth_gowin -top $(TOP) -json $(TOP).json"
+
+$(TOP).asc: $(TOP).json tangnano20k.cst
+	nextpnr-gowin --json $(TOP).json --device $(DEVICE) --cst tangnano20k.cst --write $(TOP).asc
+
+$(TOP).fs: $(TOP).asc
+	gowin_pack $(TOP).asc $(TOP).fs
+
+prog: $(TOP).fs
+	openFPGALoader -b tangnano20k $(TOP).fs
+
+clean:
+	rm -f $(TOP).json $(TOP).asc $(TOP).fs
+
+.PHONY: all prog clean