Add initial design files for 27 MHz clock counter

- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.

Introduction/counter/counter.v

@@ -1,12 +1,12 @@
 module counter (
     input wire clk,
-    input wire rst,
+    input wire btn1,
     output reg [3:0] count
     );
 
     always @(posedge clk)
     begin
-        if(rst)
+        if(btn1)
             count <= 4'b0000;
         else
             count <= count + 1;