Add initial design files for 27 MHz clock counter

- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.

Introduction/counter/dump.vcd

@@ -1,5 +1,5 @@
 $date
-	Sat Mar 22 10:16:37 2025
+	Mon Apr 14 15:59:40 2025
 $end
 $version
 	Icarus Verilog