forked from tanchou/Verilog
Add initial design files for 27 MHz clock counter
- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs. - Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.
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14
Introduction/counter/tangnano20k.cst
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14
Introduction/counter/tangnano20k.cst
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# Horloge 27 MHz (souvent sur PIN4)
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IO_LOC "clk" 4;
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IO_PORT "clk" IO_TYPE=LVCMOS33;
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# Bouton KEY1 (utilisé ici comme btn1 pour reset)
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IO_LOC "btn1" 88;
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IO_PORT "btn1" IO_TYPE=LVCMOS33;
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# LEDs (pour afficher le compteur)
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IO_LOC "count[0]" 15;
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IO_LOC "count[1]" 16;
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IO_LOC "count[2]" 17;
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IO_LOC "count[3]" 18;
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IO_PORT "count[3:0]" IO_TYPE=LVCMOS33;
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