Add initial design files for 27 MHz clock counter

- Created tangnano20k.cst to define I/O locations for clock, button, and LEDs.
- Implemented top.v module to instantiate the counter with clock and button inputs, and 4-bit count output.

README.md

@@ -1,2 +1,6 @@
 # Verilog
 
+## Command
+### Upload on fpga
+yosys -p "synth_ecp5 -json design.json" counter.v
+nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc