Remove unnecessary blank line in dht11_interface module

2025-05-27 10:31:52 +02:00
parent 7d7a6e16d8
commit 68000def79
1 changed files with 0 additions and 1 deletions
--- a/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
+++ b/Semaine_7/DHT11_UART/IP/verilog/dht11_interface.v
@@ -34,7 +34,6 @@ module dht11_interface #(
    reg sig_in;

    assign io_dht11_sig = sig_dir ? sig_out : 1'bz; // Si sig_dir = 1, on force la valeur de sig_out sur la ligne, sinon on laisse la ligne libre (1'bz)
-     

    // === REGISTRES ===
    reg [3:0] state;