forked from tanchou/Verilog
Add testbench for top_ultrasonic_led module
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the functionality of the `top_ultrasonic_led` module. - Included necessary signal definitions and event triggers for clock, reset, start, echo, and trigger signals. - Implemented a state machine to handle the ultrasonic measurement process and LED display logic. - Added simulation parameters for distance measurement and LED control. - Integrated VPI calls for waveform dumping and simulation control.
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module ultrasonic_fpga #(
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parameter integer CLK_FREQ = 27_000_000 // Fréquence d'horloge en Hz
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)(
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input wire clk,
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input wire rst,
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input wire start,
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inout wire sig, // Broche bidirectionnelle vers le capteur
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output reg [15:0] distance_cm // Distance mesurée en cm
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);
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reg [2:0] state;
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reg [15:0] trig_counter;
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reg [31:0] echo_counter;
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reg sig_out;
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reg sig_dir; // 1: output, 0: input
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assign sig = sig_dir ? sig_out : 1'bz;
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wire sig_in = sig;
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localparam IDLE = 3'd0,
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TRIG_HIGH = 3'd1,
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TRIG_LOW = 3'd2,
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WAIT_ECHO = 3'd3,
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MEASURE_ECHO = 3'd4,
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DONE = 3'd5;
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localparam integer TRIG_PULSE_CYCLES = CLK_FREQ / 100_000; // 10us pulse
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localparam integer DIST_DIVISOR = (58 * CLK_FREQ) / 1_000_000; // pour conversion us -> cm
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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state <= IDLE;
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trig_counter <= 0;
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echo_counter <= 0;
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sig_out <= 0;
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sig_dir <= 0;
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distance_cm <= 0;
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end else begin
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case (state)
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IDLE: begin
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sig_out <= 0;
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sig_dir <= 1;
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if (start) begin
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state <= TRIG_HIGH;
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trig_counter <= 0;
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end
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end
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TRIG_HIGH: begin
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sig_out <= 1;
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sig_dir <= 1;
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if (trig_counter < TRIG_PULSE_CYCLES) begin
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trig_counter <= trig_counter + 1;
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end else begin
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trig_counter <= 0;
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state <= TRIG_LOW;
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end
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end
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TRIG_LOW: begin
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sig_out <= 0;
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sig_dir <= 0; // Mettre en entrée
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state <= WAIT_ECHO;
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end
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WAIT_ECHO: begin
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if (sig_in) begin
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echo_counter <= 0;
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state <= MEASURE_ECHO;
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end
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end
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MEASURE_ECHO: begin
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if (sig_in) begin
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echo_counter <= echo_counter + 1;
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end else begin
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distance_cm <= (echo_counter * 1000) / DIST_DIVISOR;
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state <= DONE;
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end
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end
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DONE: begin
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state <= IDLE;
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end
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endcase
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end
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end
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endmodule
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