forked from tanchou/Verilog
6dfd8768a0
- Created a new testbench file `top_ultrasonic_led_tb.vvp` to simulate the functionality of the `top_ultrasonic_led` module. - Included necessary signal definitions and event triggers for clock, reset, start, echo, and trigger signals. - Implemented a state machine to handle the ultrasonic measurement process and LED display logic. - Added simulation parameters for distance measurement and LED control. - Integrated VPI calls for waveform dumping and simulation control.
Verilog
Commands
Compile code iverilog -o Nom_de_sortie.vvp .\source1.v .\tb_1.v
Upload on fpga
yosys -p "synth_ecp5 -json design.json" counter.v nextpnr-gowin --chip GW2AR-LV18QN88C8/I7 --json design.json --asc design.asc